Abstract: A method of selecting a plurality of lithography process parameters for patterning a layout on a wafer includes simulating how the layout will print on the wafer for a plurality of resolution enhancement techniques (RETs), where each RET corresponds to a plurality of lithography process parameters. For each RET, the edges of structures within the simulated layout can be classified based on manufacturability. RETs that provide optimal manufacturability can be selected. In this manner, the simulation tool can be used to determine the optimal combination of scanner setup and reticle type for minimizing the variation in wafer critical dimension (CD).

Abstract: A method of adjusting a reticle layout to correct for flare can include determining a localized reticle pattern density across the reticle layout and determining a relationship between reticle pattern density and edge adjustment for the photolithography apparatus being used. For a given feature of the reticle layout, an edge of the feature can be adjusted by a given amount based on the localized reticle pattern density adjacent the given feature. This method allows for a rule-based optical proximity correction (OPC) approach to compensate for long-range and short-range flare within a photolithography apparatus.

Abstract: A method of automatically creating and/or optimizing an optical proximity correction (OPC) rule set can include providing an initial OPC rule set and applying the initial OPC rule set to a layout data set to generate a corrected layout data set. The corrected data set can be simulated and optical rule checking (ORC) can be performed. Based on the simulation and ORC, it can be determined whether residual edge placement errors are present within the corrected layout data set and whether the residual errors lie outside specified limits. If residual edge placement errors are present within the corrected layout data set or lie outside of specified limits, existing OPC rules can be modified and/or new OPC rules can be added to the initial OPC rule set to correct the residual edge placement errors.

Abstract: A method of selecting a plurality of lithography process parameters for patterning a layout on a wafer includes simulating how the layout will print on the wafer for a plurality of resolution enhancement techniques (RETs), where each RET corresponds to a plurality of lithography process parameters. For each RET, the edges of structures within the simulated layout can be classified based on manufacturability. RETs that provide optimal manufacturability can be selected. In this manner, the simulation tool can be used to determine the optimal combination of scanner setup and reticle type for minimizing the variation in wafer critical dimension (CD).

Abstract: A method of generating a metrology recipe includes identifying regions of interest within a device layout. A coordinate list, which corresponds to the identified regions of interest, can be provided and used to create a clipped layout, which can be represented by a clipped layout data file. The clipped layout data file and corresponding coordinate list can be provided and converted into a metrology recipe for guiding one or more metrology instruments in testing a processed wafer and/or reticle. The experimental metrology results received in response to the metrology request can be linked to corresponding design data and simulation data and stored in a queriable database system.

Abstract: A method of making a device using a lithographic system having a lens from which an exposure pattern is emitted. A conforming immersion medium can be positioned between a photo resist layer and the lens. The photo resist layer, which can be disposed over a wafer, and the lens can be brought into intimate contact with the conforming immersion medium. The photo resist can then be exposed with the exposure pattern so that the exposure pattern traverses the conforming immersion medium.

Abstract: A film stack for forming shallow trench isolation among transistors and other devices on a semiconductor substrate is provided, including a plurality of light absorbing layers alternating between a layer of SiON and a layer of SiO2 and having a combined extinction coefficient >0.5. As reflected light interacts with the light absorbing layers, a substantial amount of light is absorbed therein thereby blocking such reflected light from negatively interfering with patterning of the photoresist during photo-lithography. Following patterning of the photoresist, isolation trenches may be formed in the semiconductor substrate by etching through the light absorbing layers and into the semiconductor substrate in accordance with the pattern formed on the photoresist.

Abstract: A method and apparatus for preventing contamination in a lithographic apparatus including a projection system, including providing the lithographic apparatus including the projection system for imaging an irradiated portion of a mask onto a target portion of a substrate and placing a pellicle over a surface of the projection system to inhibit contamination of the surface.

Abstract: A phase-shifting mask for a photolithographic process includes a transparent material having first and second trenches. The first trench has a first depth and the second trench has a second depth deeper than the first depth. The phase-shifting mask is suitable for testing the effect of lights of two wavelengths on a layer of photoresist.

Abstract: Shallow trench isolation among transistors and other devices on a semiconductor substrate is provided by initially forming a plurality of light absorbing layers having a combined extinction coefficient >0.5. As reflected light passes through the light absorbing layers, a substantially amount of light is absorbed therein thereby blocking such reflected light from negatively interfering with patterning of the photoresist during photo-lithography. Following patterning of the photoresist, isolation trenches are formed in the semiconductor substrate by etching through the light absorbing layers and into the semiconductor substrate in accordance with the pattern formed on the photoresist.

Abstract: A method of fabricating a feature of an integrated circuit in a layer of material includes providing a layer of photoresist having a first thickness over the layer of material; forming apertures in the layer of photoresist; growing the layer of photoresist to a second thickness greater than the first thickness; and etching the layer of material through the apertures to fabricate a feature.

Abstract: A method of developing a photoresist layer on a semiconductor wafer in a developing chamber includes applying a developer to the photoresist layer, applying an alcohol rinse to the photoresist layer, and drying the wafer.

Abstract: Shallow trench isolation among transistors and other devices on a semiconductor substrate is provided by initially forming a layer of highly absorbing silicon rich nitride to serve as a hardmask between a semiconductor substrate and a photoresist. The highly absorbing layer of silicon rich nitride has an extinction coefficient (k)>0.5. As reflected light passes through the layer of silicon rich nitride, a substantially amount of light is absorbed therein thereby blocking such reflected light from negatively interfering with patterning of the photoresist during photo-lithography. Following patterning of the photoresist, isolation trenches are formed in the semiconductor substrate by etching through the silicon rich nitride in accordance with the pattern formed on the photoresist.

Abstract: A method of fabricating a feature of an integrated circuit in a layer of material includes providing a layer of photoresist over the layer of material; exposing the layer of photoresist to a source of radiation to form an aperture therein, wherein the aperture has a wall; providing a self-assembled monolayer on at least a portion of the wall, wherein the self-assembled monolayer masks a portion of the layer of material; and etching the layer of material to form a feature, whereby the self-assembled monolayer prevents the portion of the layer of material from being etched.

Abstract: A method of fabricating an ultra narrow gate electrode for an FET and/or a conductive line in an integrated circuit by first forming a mask for the gate electrode and/or conductive line on a semiconductor substrate of minimal width dimension by optical lithography and reducing the width of the mask by laser irradiation with the beam at an angle and the semiconductor substrate rotating at a high rate of speed.

Abstract: The disclosure describes an exemplary method of improving the accuracy of model-based optical proximity correction (OPC). This method can include identifying best exposure dose and best focus conditions, measuring critical dimensions at the identified conditions, measuring critical dimensions at variations from the identified conditions, and obtaining critical dimension information by averaging measured critical dimensions.

Abstract: The disclosure describes an exemplary method of using a dual layer feature on a mask in an integrated circuit fabrication process to provide for use of the mask at multiple wavelengths. This method can include providing a dual layer feature over a mask, where the dual layer feature is configured with layers of selected thicknesses which allow the mask to be used at multiple wavelengths; and subjecting the dual layer feature and the mask to a beam at one of the multiple wavelengths.

Abstract: An exemplary method of forming a contact hole having a critical dimension which is smaller than one minimum lithographic feature can include providing a photoresist layer over a layer of material in which a contact hole is to be formed, etching the photoresist layer with an aperture having a first critical dimension, providing a bacteria film on the surface of the layer of photoresist which includes lateral side walls of the aperture, and etching a contact hole in the layer of material. The bacteria film decreases the aperture in width to a second critical dimension. The contact hole has the second critical dimension.

Abstract: A method of developing a photoresist layer on a semiconductor wafer in a developing chamber includes applying a developer to the photoresist layer, applying an alcohol rinse to the photoresist layer, and drying the wafer.

Abstract: A method of inspecting a semiconductive wafer-in-process to determine the accuracy of alignment of a lower process layer to an upper process layer. In this method, a conductive target attribute is formed on a first alignment portion of the wafer-in-process. A contact attribute is formed on the upper process layer through which an electric path can be established with the target attribute in an acceptable alignment situation but cannot established in an unacceptable alignment situation. By attempting to establish an electric path from the target attribute through the contact attribute, the accuracy of alignment can be determined based on whether or not an electrical path is established. The target attribute may be a series of conductive strips and the contact attribute may be a series of contact holes that will overlay the corresponding target attributes in differing degrees in an acceptable alignment situation.