Patents by Inventor Carl P. Babcock

Carl P. Babcock has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6358843
    Abstract: A method of fabricating ultra small vias in insulating layers on a semiconductor substrate for an integrated circuit by a first exposure of a photoresist to line pattern with the semiconductor substrate in a first position and the exposure dosage being insufficient to develop the photoresist followed by a second overlapping exposure of the line pattern with the semiconductor substrate being in a position 90° from the first position and again being insufficient in exposure dosage to develop the photoresist, the overlapped line exposures creating via exposures of sufficient dosage to develop the photoresist, thereby creating a smaller via opening than with a single exposure.
    Type: Grant
    Filed: April 2, 2001
    Date of Patent: March 19, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Carl P. Babcock, Bhanwar Singh
  • Publication number: 20020009845
    Abstract: Isolation regions are formed with greater accuracy and consistency by forming an oxide-silicon nitride stack and then depositing an antireflective layer, of silicon oxime, on the silicon nitride layer before patterning. Embodiments also include depositing the silicon nitride layer and the silicon oxime layer in the same tool.
    Type: Application
    Filed: August 17, 1999
    Publication date: January 24, 2002
    Inventors: JAYENDRA D. BHAKTA, CARL P. BABCOCK
  • Patent number: 6335235
    Abstract: Isolation regions are formed with greater accuracy and consistency by forming an oxide-silicon nitride stack and then depositing an amorphous silicon antireflective layer, on the silicon nitride layer before patterning. Embodiments also include depositing the silicon nitride layer and the amorphous silicon layer in the same tool.
    Type: Grant
    Filed: August 17, 1999
    Date of Patent: January 1, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jayendra D. Bhakta, Carl P. Babcock
  • Patent number: 6255717
    Abstract: Shallow trench isolation among transistors and other devices on a semiconductor substrate is provided by initially forming a layer of highly absorbing silicon rich nitride to serve as a hardmask between a semiconductor substrate and a photoresist. The highly absorbing layer of silicon rich nitride has an extinction coefficient (k)>0.5. As reflected light passes through the layer of silicon rich nitride, a substantially amount of light is absorbed therein thereby blocking such reflected light from negatively interfering with patterning of the photoresist during photolithography. Following patterning of the photoresist, isolation trenches are formed in the semiconductor substrate by etching through the silicon rich nitride in accordance with the pattern formed on the photoresist.
    Type: Grant
    Filed: November 25, 1998
    Date of Patent: July 3, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Carl P. Babcock, Jayendra D. Bhakta