Abstract: A semiconductor memory cell comprising six vertical-transport field-effect transistors (VTFET) on a wafer. The six VTFET are in a first layer. The six VTFET are in a first row.

Abstract: Methods and systems for watermarking a circuit design include defining a watermarked cell library that includes cells, each of which defines a design structure that corresponds to a manufacturable physical structure, at least one of which being a watermarked call that includes a watermark. The watermark is encoded using a design structure that extends beyond a respective cell boundary. A first circuit design file is generated for a device to be manufactured. The first circuit design file including at least one watermarked cell. The first circuit design file is sent to a manufacturer for fabrication of a corresponding device that includes a watermark structure that encodes an identifier.

Abstract: A phase change memory (PCM) cell comprising a substrate a first electrode located on the substrate. A phase change material layer located adjacent to the first electrode, wherein a first side of the phase change material layer is in direct contact with the first electrode. A second electrode located adjacent to phase change material layer, wherein the second electrode is in direct contact with a second side of the phase change material layer, wherein the first side and the second side are different sides of the phase change material layer. An airgap is located directly above the phase change material layer, wherein the airgap provides space for the phase change material to expand or restrict.

Abstract: A phase change memory structure with improved sidewall heater and formation thereof may be presented. Phase change materials are capable of being switched between a first structural state in which the material is in a generally amorphous solid phase, and a second structural state in which the material is in a generally crystalline solid phase in the active region of the cell. Presented herein may be a side wall heater, where the upper section extends through bilayer dielectric to contact a phase change material layer and the lower section of the sidewall heater has conductive layers in contact with the bottom electrode. The width of the sidewall heater may reflect an inverted T shape reducing the current requirement to reset the phase change material.

Abstract: According to the embodiment of the present invention, a semiconductor device includes a first nanodevice and a second nanodevice. The second nanodevice is located adjacent to and parallel to the first nanodevice along a first axis. The first nanodevice and the second nanodevice each include a first section, a second section, and a third section. A first gate cut region is located between the first sections of the first nanodevice and the second nanodevice. A middle gate cut region is located between the second sections of the first nanodevice and the second nanodevice. A third gate cut region is located between the third sections of the first nanodevice and the second nanodevice. The middle gate cut region has different dimensions along a second axis than the first gate cut region and the third gate cut region. A middle section contact is located in the middle gate cut region.

Abstract: A field effect transistor (FET) cell structure of an integrated circuit (IC) is provided. The FET cell structure includes first and second adjacent cells. Each of the first and second adjacent cells spans a first layer and a second layer. The second layer is vertically stacked on the first layer. The first cell includes n-doped FETs (NFETs) on one of the first and second layers and p-doped FETs (PFETs) on another of the first and second layers. The second cell includes at least one of a number of NFETs on the one of the first and second layers differing from a number of the NFETs in the first cell and a number of PFETs on the another of the first and second layers differing from a number of the PFETs in the first cell.

Abstract: A semiconductor structure having improved performance is provided that includes a local enlarged via-to-backside power rail (VBPR) contact structure which connects a source/drain region of one field effect transistor (FET) to a backside power rail.

Abstract: A semiconductor structure is provided in which a phase change memory (PCM) device region including a PCM is located in a back side of a wafer. A PCM device back side source/drain contact structure connects the PCM to a first source/drain structure of a first field effect transistor (FET) that is present in a front side of the wafer, the second source/drain structure of the first FET is connected to a front side BEOL structure by a front side source/drain contact structure. A logic device region and/or an analog device region can be located laterally adjacent to the PCM device region. A back side power distribution network can be present in the logic device region and/or an analog device region.

Abstract: A microelectronic structure including a static random-access memory (SRAM) device that includes a plurality of stacked transistors. Each of the plurality of stacked transistors that includes a bottom transistor and an upper transistor, where the upper transistor is not in vertical alignment with the bottom transistor.

Abstract: Embodiments of present invention provide a phase change memory (PCM) device. The PCM device includes a first PCM cell with the first PCM cell including an L-shaped phase change element, the L-shaped phase change element having a horizontal portion and a vertical portion on top of the horizontal portion; a selector underneath the horizontal portion of the L-shaped phase change element; a top electrode in contact with a top surface of the vertical portion of the L-shaped phase change element; and a bottom electrode in contact with the selector; and a second PCM cell. A method of manufacturing the PCM device is also provided.

Abstract: Embodiments of present invention provide a SRAM device. The SRAM device includes a first, a second, and a third SRAM cell each having a first and a second pass-gate (PG) transistor, wherein the second PG transistor of the second SRAM cell and the first PG transistor of the first SRAM cell are stacked in a first PG transistor cell, and the first PG transistor of the third SRAM cell and the second PG transistor of the first SRAM cell are stacked in a second PG transistor cell. The first and second PG transistors of the first SRAM cell may be stacked on top of, or underneath, the second PG transistor of the second SRAM cell and/or the first PG transistor of the third SRAM cell.

Abstract: A semiconductor device is provided that includes at least one stacked FET device including two top transistors stacked over a single bottom transistor. The at least one stacked FET includes a full gate cut structure that is used to separate different device areas from each other, a top gate cut structure that used to separate the two top transistors, and a bottom gate cut structure that is used to provide the single bottom transistor. The at least one FET device can be used to provide a SRAM containing six transistors.

Abstract: Embodiments are disclosed for a complementary metal oxide semiconductor (CMOS) device. The CMOS device includes a hybrid cross-couple contact. The hybrid cross-couple contact includes a frontside contact to a gate of the CMOS device. The frontside contact is disposed on a frontside of the CMOS device. The hybrid cross-couple contact includes a source contact to a source of the CMOS device. The source contact is disposed on a backside of the CMOS device. The hybrid cross-couple contact includes a drain contact to a drain of the CMOS device. The drain contact is disposed on a backside of the CMOS device.

Abstract: Embodiments of present invention provide a SRAM device. The SRAM device includes a first, a second, and a third SRAM cell each having a first and a second pass-gate (PG) transistor, wherein the second PG transistor of the second SRAM cell and the first PG transistor of the first SRAM cell are stacked in a first PG transistor cell, and the first PG transistor of the third SRAM cell and the second PG transistor of the first SRAM cell are stacked in a second PG transistor cell. The first and second PG transistors of the first SRAM cell may be stacked on top of, or underneath, the second PG transistor of the second SRAM cell and/or the first PG transistor of the third SRAM cell.

Abstract: Embodiments of present invention provide a SRAM memory. The SRAM memory includes a frontside and a backside; a first pull-up (PU) transistor stacked over a first pull-down (PD) transistor; a second PU transistor stacked over a second PD transistor; a frontside cross-couple at the frontside, above the first and second PU transistors, that connects a first source/drain (S/D) region of the first PU transistor with a gate of the second PU transistor; and a backside cross-couple, at the backside underneath the first and second PD transistors, that connects a first S/D region of the second PD transistor with a gate of the first PD transistor. A method of manufacturing the SRAM memory is also provided.

Abstract: An approach for a nanosheet device with a single diffusion break is disclosed. The device comprises of active gate is formed above the BDI. At least the SDB is also formed over BDI with dielectric filled gate. The dielectric fill forms an indentation into the remaining nanosheets, under the spacer region, or between the inner spacers, in the SDB region. The method of creating the device comprises of, forming a gate cut opening between two ends of a dummy gate of one or more gates; forming a first sacrificial material on the gate cut opening; creating a single diffusion break; removing the dummy gate and oxide layer; removing, selectively a second sacrificial material; trimming, selectively stack of nanosheets; and forming dielectric in the gate cut opening and the single diffusion break.

Abstract: Embodiments of present invention provide a static random-access-memory (SRAM) device. The SRAM device includes a first set of nanosheets used in an n-type transistor; and a second set of nanosheets with one or more nanosheets of the second set of nanosheets used in a p-type transistor, wherein a width of the second set of nanosheets is wider than a width of the first set of nanosheets. In one embodiment the p-type transistor is used as a pull-up transistor and the n-type transistor is used as a pull-down transistor or a pass-gate transistor. A method of manufacturing the SRAM device is also provided.

Abstract: A phase change memory (PCM) semiconductor device is provided. The PCM semiconductor device includes: a phase change material stack on a substrate, the phase change material stack including at least two phase change material layers each separated by an insulating layer; a first electrode on a first side of the phase change material stack; and a second electrode on a second side of the phase change material stack, wherein a first one of the phase change material layers has a length that is different from a length of a second one of the phase change material layers.

Abstract: A phase change memory (PCM) cell comprising a substrate a first electrode located on the substrate. A phase change material layer located adjacent to the first electrode, wherein a first side of the phase change material layer is in direct contact with the first electrode. A second electrode located adjacent to phase change material layer, wherein the second electrode is in direct contact with a second side of the phase change material layer, wherein the first side and the second side are different sides of the phase change material layer. An airgap is located directly above the phase change material layer, wherein the airgap provides space for the phase change material to expand or restrict.

Abstract: The semiconductor device comprises a first ring oscillator and a second ring oscillator. An input of the first ring oscillator is an end output of the first ring oscillator and an output of the second ring oscillator and wherein an input of the second ring oscillator is an end output of the second ring oscillator and an output of the first ring oscillator.