Abstract: A semiconductor structure includes a plurality of field effect transistors formed on a substrate including p-type doped field effect transistors (pFETs) and n-type doped field effect transistors (nFETs). A self-aligned buried local interconnect electrically connects a bottom source or drain region of the pFET with an adjacent bottom source or drain region of the nFET. The self-aligned buried local interconnect is serially aligned with and intermediate opposing ends of a gate electrode. Other embodiments include methods for forming the buried local interconnect.

Abstract: A method for using a distributed memory device in a memory augmented neural network system includes receiving, by a controller, an input query to access data stored in the distributed memory device, the distributed memory device comprising a plurality of memory banks. The method further includes determining, by the controller, a memory bank selector that identifies a memory bank from the distributed memory device for memory access, wherein the memory bank selector is determined based on a type of workload associated with the input query. The method further includes computing, by the controller and by using content based access, a memory address in the identified memory bank. The method further includes generating, by the controller, an output in response to the input query by accessing the memory address.

Abstract: Power distribution fabrics and methods of forming the same include forming a first layer of parallel conductive lines, having a first width. At least one additional layer of conductive lines is formed over the first layer of conductive lines, with the conductive lines of each successive layer in the at least one additional layer having a different orientation and a different width relative to the conductive lines of the preceding layer.

Abstract: A method for fabricating a semiconductor device includes forming conductive material on a first metallization level including at least one via disposed on at least one conductive line, subtractively patterning the conductive material to form at least one conductive layer corresponding to at least one conductive line of a second metallization level misaligned with the at least one via of the first metallization level, and at least one cavity within the at least one via forming at least one damaged via resulting from the misalignment, and filling the at least one cavity with conductive liner material to form a filled cavity to repair the at least one damaged via.

Abstract: A method is presented for employing double-patterning to reduce via-to-via spacing. The method includes forming a mandrel layer over a substrate, forming sacrificial hardmask layers over the mandrel layer defining a litho stack, creating a pattern in the litho stack, the pattern having a narrow section connecting two wider sections to define a substantially hour-glass shape, depositing a spacer assuming a shape of the pattern, and etching the litho stack to expose the mandrel layer and metal lines, wherein the metals lines define sharp distal ends reducing a distance between the metal lines.

Abstract: A method is presented for forming an on-chip security key. The method includes electrically connecting a pair of phase change memory (PCM) elements in series, electrically connecting a programming transistor to the pair of PCM elements, electrically connecting an input of an inverter to a common node of the pair of PCM elements, setting the PCM elements to a low resistance state (LRS) in an initialization stage, applying a RESET pulse to generate a security bit and to cause one of the PCM elements to change to a high resistance state (HRS), and generating a logic “1” or “0” at the output of the inverter.

Abstract: A method may include filling a via opening with a spacer, the via opening formed in a dielectric layer, forming a trench within the spacer, filling the trench with a metal layer, recessing the spacer to form an opening and expose an upper portion of the metal layer, wherein the exposed portion of the metal layer is formed into a cone shaped tip, conformally depositing a liner along a bottom and a sidewall of the opening and the exposed portion of the metal layer, depositing a second dielectric layer along the bottom of the opening on top of the liner, recessing the liner to form a channel and partially exposing a sidewall of the second dielectric layer and a sidewall of the metal layer, depositing a third dielectric layer in the channel, and depositing a phase change memory layer within the opening.

Abstract: A method is presented for forming a multi-level of interconnects underneath a complementary metal oxide semiconductor (CMOS) device. The method includes forming a stack including alternating layers of a semiconductor material and a first conductive material, patterning vias in the stack to define multiple stacks, depositing a first block material within each of the vias, forming a series of first block materials within a first via, forming a series of second block materials within a second via, the first and second vias being on opposed ends of a stack of the multiple stacks, and performing vertical metallization between the first block material and the series of first block materials in the first via, and between the first block material and the series of second block materials in the second via.

Abstract: A method may include filling a via opening with a spacer, the via opening formed in a dielectric layer, forming a trench within the spacer, filling the trench with a metal layer, recessing the spacer to form an opening and expose an upper portion of the metal layer, wherein the exposed portion of the metal layer is formed into a cone shaped tip, conformally depositing a liner along a bottom and a sidewall of the opening and the exposed portion of the metal layer, depositing a second dielectric layer along the bottom of the opening on top of the liner, recessing the liner to form a channel and partially exposing a sidewall of the second dielectric layer and a sidewall of the metal layer, depositing a third dielectric layer in the channel, and depositing a phase change memory layer within the opening.

Abstract: A first TS is coupled to first S/D over first fin, second TS coupled to second S/D over first fin, third TS coupled to third S/D over second fin, fourth TS coupled to fourth S/D over second fin, gate metal over first and second fins, and gate cap over gate metal. First TS cap is on first TS, second TS cap on second TS, third TS cap on third TS, and fourth TS cap on fourth TS. ILD is formed on top of gate cap and first through fourth TS caps. First opening is through ILD and second TS cap such that part of gate metal is exposed, after removing part of gate cap. Second opening is through ILD to expose another part of gate metal. Combined gate metal contact and local metal connection is formed in first opening and individual gate metal contact is formed in second opening.

Abstract: A method of fabricating a static random-access memory (SRAM) device includes forming a sacrificial material and replacing the sacrificial material with a metal to form a cross-couple contact on a metal gate stack. A portion of the metal gate stack directly contacts each of a sidewall and an endwall of the cross-couple contact.

Abstract: Vertical GAA FET structures are disclosed in which a current-carrying nanowire is oriented substantially perpendicular to the surface of a silicon substrate. The vertical GAA FET is intended to meet design and performance criteria for the 7 nm technology generation. In some embodiments, electrical contacts to the drain and gate terminals of the vertically oriented GAA FET can be made via the backside of the substrate. Examples are disclosed in which various n-type and p-type transistor designs have different contact configurations. In one example, a backside gate contact extends through the isolation region between adjacent devices. Other embodiments feature dual gate contacts for circuit design flexibility. The different contact configurations can be used to adjust metal pattern density.

Abstract: A semiconductor device includes a base structure including a lower level via and a lower level dielectric layer, a conductive pillar including an upper level line and an upper level via disposed on the lower level via, and a protective structure disposed between the lower level via and the upper level line. The protective structure includes a material having an etch rate less than or equal to that of the lower level via.

Abstract: A method of forming a semiconductor structure includes forming fins over a substrate, forming a shallow trench isolation region over the substrate surrounding the fins, and forming nanosheet stacks providing channels for nanosheet field-effect transistors. The method also includes forming a channel protecting liner over a portion of sidewalls and a top surface of a first nanosheet stack formed over a first fin, the channel protecting liner being further formed over a portion of the shallow trench isolation region extending from the sidewalls of the first nanosheet stack toward a second nanosheet stack formed over a second fin. The method further includes forming gate stacks surrounding exposed portions of the nanosheet stacks, forming an asymmetric self-aligned gate isolation structure over the channel protecting liner, and forming a symmetric self-aligned gate isolation structure over a portion of the shallow trench isolation region between a third fin and a fourth fin.

Abstract: A technique relates to a semiconductor device. A first stack includes a first plurality of nanowires respectively coupled to first source and drain regions, and a second stack includes a second plurality of nanowires respectively coupled to second source and drain regions. First source and drain contacts couple to a first predefined number of the first plurality of nanowires. Second source and drain contacts to couple to a second predefined number of the second plurality of nanowires, wherein the first predefined number is different from the second predefined number.

Abstract: A semiconductor device is formed to include a fin structure, a first trench at a first lateral end of the fin, a second trench at a second lateral end of the fin, and a filler filled on a first traverse side of the fin and a second traverse side of the fin. The filler is contained between the first trench and the second trench, and oxidized in-place to cause a stress to be exerted on the first and second traverse sides of the fin, the stress causing the fin to exhibit a tensile strain in a lateral running direction of the fin.

Abstract: A semiconductor structure includes a plurality of field effect transistors formed on a substrate including p-type doped field effect transistors (pFETs) and n-type doped field effect transistors (nFETs). A self-aligned buried local interconnect electrically connects a bottom source or drain region of the pFET with an adjacent bottom source or drain region of the nFET. The self-aligned buried local interconnect is serially aligned with and intermediate opposing ends of a gate electrode. Other embodiments include methods for forming the buried local interconnect.

Abstract: A technique relates to a semiconductor device. A first stack includes a first plurality of nanowires respectively coupled to first source and drain regions, and a second stack includes a second plurality of nanowires respectively coupled to second source and drain regions. First source and drain contacts couple to a first predefined number of the first plurality of nanowires. Second source and drain contacts to couple to a second predefined number of the second plurality of nanowires, wherein the first predefined number is different from the second predefined number.

Abstract: Ultra-low-k dielectric materials used as inter-layer dielectrics in high-performance integrated circuits are prone to be structurally unstable. The Young's modulus of such materials is decreased, resulting in porosity, poor film strength, cracking, and voids. An alternative dual damascene interconnect process incorporates air gaps into a high modulus dielectric material to maintain structural stability while reducing capacitance between adjacent nanowires. Incorporation of an air gap having k=1.0 compensates for the use of a higher modulus film having a dielectric constant greater than the typical ultra-low-k (ULK) dielectric value of about 2.2. The higher modulus film containing the air gap is used as an insulator between adjacent metal lines, while a ULK film is retained to insulate vias. The dielectric layer between two adjacent metal lines thus forms a ULK/high-modulus dielectric bi-layer.

Abstract: A first TS is coupled to first S/D over first fin, second TS coupled to second S/D over first fin, third TS coupled to third S/D over second fin, fourth TS coupled to fourth S/D over second fin, gate metal over first and second fins, and gate cap over gate metal. First TS cap is on first TS, second TS cap on second TS, third TS cap on third TS, and fourth TS cap on fourth TS. ILD is formed on top of gate cap and first through fourth TS caps. First opening is through ILD and second TS cap such that part of gate metal is exposed, after removing part of gate cap. Second opening is through ILD to expose another part of gate metal. Combined gate metal contact and local metal connection is formed in first opening and individual gate metal contact is formed in second opening.