Abstract: A junction diode array is disclosed for use in protecting integrated circuits from electrostatic discharge. The junction diodes integrate symmetric and asymmetric junction diodes of various sizes and capabilities. Some of the junction diodes are configured to provide low voltage and current discharge via un-encapsulated interconnecting wires, while others are configured to provide high voltage and current discharge via encapsulated interconnecting wires. Junction diode array elements include p-n junction diodes and N+/N++ junction diodes. The junction diodes include implanted regions having customized shapes. If both symmetric and asymmetric diodes are not needed as components of the junction diode array, the array is configured with isolation regions between diodes of either type. Some junction diode arrays include a buried oxide layer to prevent diffusion of dopants into the substrate beyond a selected depth.

Abstract: Nanoscale efuses, antifuses, and planar coil inductors are disclosed. A copper damascene process can be used to make all of these circuit elements. A low-temperature copper etch process can be used to make the efuses and efuse-like inductors. The circuit elements can be designed and constructed in a modular fashion by linking a matrix of metal columns in different configurations and sizes. The number of metal columns, or the size of a dielectric mesh included in the circuit element, determines its electrical characteristics. Alternatively, the efuses and inductors can be formed from interstitial metal that is either deposited into a matrix of dielectric columns, or left behind after etching columnar openings in a block of metal. Arrays of metal columns also serve a second function as features that can improve polish uniformity in place of conventional dummy structures. Use of such modular arrays provides flexibility to integrated circuit designers.

Abstract: Metal interconnections are formed in an integrated by combining damascene processes and subtractive metal etching. A wide trench is formed in a dielectric layer. A conductive material is deposited in the wide trench. Trenches are etched in the conductive material to delineate a plurality of metal plugs each contacting a respective metal track exposed by the wide trench.

Abstract: An integrated circuit die includes a semiconductor substrate, a first dielectric layer on the substrate, and a second dielectric layer on the first dielectric layer. Trenches are formed in the first and second dielectric layers. Metal interconnection tracks are formed on sidewalls of the trench on the exposed portions of the second dielectric layer.

Abstract: A semiconductor device having a gate positioned in a recess between the source region and a drain region that are adjacent either side of the gate electrode. A channel region is below a majority of the source region as well as a majority of the drain region and the entire gate electrode.

Abstract: The present disclosure is directed to a device that includes a first substrate having a first plurality of hollow pillars on the first substrate and a first plurality of channels in the first substrate coupled to the first plurality of hollow pillars. The device includes a second substrate attached to the first substrate, the second substrate having a second plurality of hollow pillars on the second substrate and a second plurality of channels in the second substrate coupled to the second plurality of hollow pillars, the first plurality of hollow pillars being coupled to the second plurality of hollow pillars to allow a fluid medium to move through the substrate to cool the first substrate and the second substrate.

Abstract: Metal interconnections are formed in an integrated by combining damascene processes and subtractive metal etching. A wide trench is formed in a dielectric layer. A conductive material is deposited in the wide trench. Trenches are etched in the conductive material to delineate a plurality of metal plugs each contacting a respective metal track exposed by the wide trench.

Abstract: A junction diode array for use in protecting integrated circuits from electrostatic discharge can be fabricated to include symmetric and/or asymmetric junction diodes of various sizes. The diodes can be configured to provide low voltage and current discharge via unencapsulated contacts, or high voltage and current discharge via encapsulated contacts. Use of tilted implants in fabricating the junction diode array allows a single hard mask to be used to implant multiple ion species. Furthermore, a different implant tilt angle can be chosen for each species, along with other parameters, (e.g., implant energy, implant mask thickness, and dimensions of the mask openings) so as to craft the shape of the implanted regions. Isolation regions can be inserted between already formed diodes, using the same implant hard mask if desired. A buried oxide layer can be used to prevent diffusion of dopants into the substrate beyond a selected depth.

Abstract: A semiconductor device having a gate positioned in a recess between the source region and a drain region that are adjacent either side of the gate electrode. A channel region is below a majority of the source region as well as a majority of the drain region and the entire gate electrode.

Abstract: A plurality of metal tracks are formed in an integrated circuit die in three metal layers stacked within the die. A protective dielectric layer is formed around metal tracks of an intermediate metal layer. The protective dielectric layer acts as a hard mask to define contact vias between metal tracks in the metal layers above and below the intermediate metal layer.

Abstract: A plurality of metal tracks are formed in a plurality of intermetal dielectric layers stacked in an integrated circuit die. Thin protective dielectric layers are formed around the metal tracks. The protective dielectric layers act as a hard mask to define contact vias between metal tracks in the intermetal dielectric layers.

Abstract: A semiconductor device having a gate positioned in a recess between the source region and a drain region that are adjacent either side of the gate electrode. A channel region is below a majority of the source region as well as a majority of the drain region and the entire gate electrode.

Abstract: A method for manufacturing a photovoltaic solar cell device includes the following. A p-n junction having a first doping density is formed. Formation of the p-n junction is enhanced by introducing a second doping density to form high doped areas for a dual emitter application. The high doped areas are defined by a masking process integrated with the formation of the p-n junction, resulting in a mask pattern of the high doped areas. A metallization of the high doped areas occurs in accordance with the mask pattern of the high doped areas.

Abstract: A method for manufacturing one or more electrically contactable grids on at least one surface of a semiconductor substrate for use in a solar cell product includes the following. A heat-sensitive masking agent layer is deposited on the surface of the substrate of the solar cell product. The masking agent layer is locally heated to form a grid mask. Selected parts of the masking agent layer defined by locally heating are removed to form openings in the grid mask. A contact metallization is applied on the grid mask.

Abstract: An aluminum lateral interconnect of a Back End of the Line (BEOL) is used to define the x and y dimensions of a through-silicon via in a semiconductor chip formed in a silicon substrate. The TSV includes one or more aluminum annulus formed on a surface of the substrate, and a deep trench in the substrate having a diameter that is determined by the diameter of the aluminum annulus. The annulus can also be provided with a conductive strap upon which a capacitor can be formed. The strap can also be used to provide a connection of the TSV to other BEOL interconnects.

Abstract: A semiconductor device having a gate positioned in a recess between the source region and a drain region that are adjacent either side of the gate electrode. A channel region is below a majority of the source region as well as a majority of the drain region and the entire gate electrode.

Abstract: A transistor device and method of forming the same comprises a substrate; a first gate electrode over the substrate; a second gate electrode over the substrate; and a landing pad comprising a pair of flanged ends overlapping the second gate electrode, wherein the structure of the second gate electrode is discontinuous with the structure of the landing pad.

Abstract: In one embodiment, Hexagonal tiles encompassing a large are divided into three groups, each containing ? of all hexagonal tiles that are disjoined among one another. Openings for the hexagonal tiles in each group are formed in a template layer, and a set of self-assembling block copolymers is applied and patterned within each opening. This process is repeated three times to encompass all three groups, resulting in a self-aligned pattern extending over a wide area. In another embodiment, the large area is divided into rectangular tiles of two non-overlapping and complementary groups. Each rectangular area has a width less than the range of order of self-assembling block copolymers. Self-assembled self-aligned line and space structures are formed in each group in a sequential manner so that a line and space pattern is formed over a large area extending beyond the range of order.

Abstract: A first nanoscale self-aligned self-assembled nested line structure having a sublithographic width and a sublithographic spacing and running along a first direction is formed from first self-assembling block copolymers within a first layer. The first layer is filled with a filler material and a second layer is deposited above the first layer containing the first nanoscale nested line structure. A second nanoscale self-aligned self-assembled nested line structure having a sublithographic width and a sublithographic spacing and running in a second direction is formed from second self-assembling block copolymers within the second layer. The composite pattern of the first nanoscale nested line structure and the second nanoscale nested line structure is transferred into an underlayer beneath the first layer to form an array of structures containing periodicity in two directions.

Abstract: In one embodiment, Hexagonal tiles encompassing a large are divided into three groups, each containing ? of all hexagonal tiles that are disjoined among one another. Openings for the hexagonal tiles in each group are formed in a template layer, and a set of self-assembling block copolymers is applied and patterned within each opening. This process is repeated three times to encompass all three groups, resulting in a self-aligned pattern extending over a wide area. In another embodiment, the large area is divided into rectangular tiles of two non-overlapping and complementary groups. Each rectangular area has a width less than the range of order of self-assembling block copolymers. Self-assembled self-aligned line and space structures are formed in each group in a sequential manner so that a line and space pattern is formed over a large area extending beyond the range of order.