Patents by Inventor Carl Ramey

Carl Ramey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11409045
    Abstract: Methods and apparatus for tuning a photonics-based component. An opto-electrical detector is configured to output an electrical signal based on a measurement of light intensity of the photonics-based component, the light intensity being proportional to an amount of detuning of the photonics-based component. Analog-to-digital conversion (ADC) circuitry is configured to output a digital signal based on the electrical signal output from the opto-electrical detector. Feedback control circuitry is configured to tune the photonics-based component based, at least in part, on the digital signal output from the ADC circuitry.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: August 9, 2022
    Assignee: Lightmatter, Inc.
    Inventors: Carlos Dorta-Quinones, Carl Ramey, Omer Ozgur Yildirim, Chithira Ravi, Shashank Gupta, Nicholas C. Harris
  • Patent number: 11398871
    Abstract: Systems and methods for performing signed matrix operations using a linear photonic processor are provided. The linear photonic processor is formed as an array of first amplitude modulators and second amplitude modulators, the first amplitude modulators configured to encode elements of a vector into first optical signals and the second amplitude modulators configured to encode a product between the vector elements and matrix elements into second optical signals. An apparatus may be used to implement a signed value of an output of the linear processor. The linear photonic processor may be configured to perform matrix-vector and/or matrix-matrix operations.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: July 26, 2022
    Assignee: Lightmatter, Inc.
    Inventors: Darius Bunandar, Nicholas C. Harris, Michael Gould, Carl Ramey, Tomo Lazovich
  • Patent number: 11367711
    Abstract: A memory device is described. The memory device comprises a plurality of stacked memory layers, wherein each of the plurality of stacked memory layers comprises a plurality of memory cells. The memory device further comprises an optical die bonded to the plurality of stacked memory layers and in electrical communication with the stacked memory layers through one or more interconnects. The optical die comprises an optical transceiver, and a memory controller configured to control read and/or write operations of the stacked memory layers. The optical die may be positioned at one end of the plurality of stacked memory layers. The one or more interconnects may comprise one or more through silicon vias (TSV). The plurality of memory cells may comprise a plurality of solid state memory cells. The memory devices described herein can enable all-to-all, point-to-multipoint and ring architectures for connecting logic units with memory devices.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: June 21, 2022
    Assignee: Lightmatter, Inc.
    Inventors: Nicholas C. Harris, Carl Ramey
  • Publication number: 20220094443
    Abstract: Aspects relate to a photonic processing system, a photonic processor, and a method of performing matrix-vector multiplication. An optical encoder may encode an input vector into a first plurality of optical signals. A photonic processor may receive the first plurality of optical signals; perform a plurality of operations on the first plurality of optical signals, the plurality of operations implementing a matrix multiplication of the input vector by a matrix; and output a second plurality of optical signals representing an output vector. An optical receiver may detect the second plurality of optical signals and output an electrical digital representation of the output vector.
    Type: Application
    Filed: December 1, 2021
    Publication date: March 24, 2022
    Applicant: Lightmatter, Inc.
    Inventors: Darius Bunandar, Nicholas C. Harris, Carl Ramey
  • Patent number: 11256029
    Abstract: Photonic packages are described. One such photonic package includes a photonic chip, an application specific integrated circuit, and optionally, an interposer. The photonic chip includes photonic microelectromechanical system (MEMS) devices. A photonic package may include a material layer patterned to include recesses. The recesses are aligned with the photonic MEMS devices so as to form enclosed cavities around the photonic MEMS devices. This arrangement preserves the integrity of the photonic MEMS devices.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: February 22, 2022
    Assignee: Lightmatter, Inc.
    Inventors: Sukeshwar Kannan, Carl Ramey, Michael Gould, Nicholas C. Harris
  • Publication number: 20220029730
    Abstract: Systems and methods for increasing throughput of a photonic processor by using photonic degrees of freedom (DOF) are provided. The photonic processor includes a multiplexer configured to multiplex, using at least one photonic DOF, multiple encoded optical signals into a multiplexed optical signal. The photonic processor also includes a detector coupled to an output of an optical path including the multiplexer, the detector being configured to generate a first current based on the multiplexed optical signal or a demultiplexed portion of the multiplexed optical signal. The photonic processor further includes a modulator coupled to and output of the detector, the modulator being configured to generate a second current by modulating the first current.
    Type: Application
    Filed: July 23, 2021
    Publication date: January 27, 2022
    Applicant: Lightmatter, Inc.
    Inventors: Darius Bunandar, Michael Gould, Nicholas C. Harris, Carl Ramey
  • Patent number: 11218227
    Abstract: Aspects relate to a photonic processing system, a photonic processor, and a method of performing matrix-vector multiplication. An optical encoder may encode an input vector into a first plurality of optical signals. A photonic processor may receive the first plurality of optical signals; perform a plurality of operations on the first plurality of optical signals, the plurality of operations implementing a matrix multiplication of the input vector by a matrix; and output a second plurality of optical signals representing an output vector. An optical receiver may detect the second plurality of optical signals and output an electrical digital representation of the output vector.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: January 4, 2022
    Assignee: Lightmatter, Inc.
    Inventors: Darius Bunandar, Nicholas C. Harris, Carl Ramey
  • Publication number: 20210405682
    Abstract: Hybrid analog-digital processing systems are described. An example of a hybrid analog-digital processing system includes photonic accelerator configured to perform matrix-vector multiplication using light. The photonic accelerator exhibits a frequency response having a first bandwidth (e.g., less than 3 GHz). The hybrid analog-digital processing system further includes a plurality of analog-to-digital converters (ADCs) coupled to the photonic accelerator, and a plurality of digital equalizers coupled to the plurality of ADCs, wherein the digital equalizers are configured to set a frequency response of the hybrid analog-digital processing system to a second bandwidth greater than the first bandwidth.
    Type: Application
    Filed: June 25, 2021
    Publication date: December 30, 2021
    Applicant: Lightmatter, Inc.
    Inventors: Michael Gould, Carl Ramey, Nicholas C. Harris, Darius Bunandar
  • Publication number: 20210365240
    Abstract: Photonic processors are described. The photonic processors described herein are configured to perform matrix-matrix (e.g., matrix-vector) multiplication. Some embodiments relate to photonic processors arranged according to a dual-rail architecture, in which numeric values are encoded in the difference between a pair optical signals (e.g., in the difference between the powers of the optical signals). Relative to other architectures, these photonic processors exhibit increased immunity to noise. Some embodiments relate to photonic processors including modulatable detector-based multipliers. Modulatable detectors are detectors designed so that the photocurrent can be modulated according to an electrical control signal. Photonic processors designed using modulatable detector-based multipliers are significantly more compact than other types of photonic processors.
    Type: Application
    Filed: August 10, 2021
    Publication date: November 25, 2021
    Applicant: Lightmatter, Inc.
    Inventors: Nicholas C. Harris, Darius Bunandar, Michael Gould, Carl Ramey, Shashank Gupta, Carlos Dorta-Quinones
  • Patent number: 11169780
    Abstract: Photonic processors are described. The photonic processors described herein are configured to perform matrix-matrix (e.g., matrix-vector) multiplication. Some embodiments relate to photonic processors arranged according to a dual-rail architecture, in which numeric values are encoded in the difference between a pair optical signals (e.g., in the difference between the powers of the optical signals). Relative to other architectures, these photonic processors exhibit increased immunity to noise. Some embodiments relate to photonic processors including modulatable detector-based multipliers. Modulatable detectors are detectors designed so that the photocurrent can be modulated according to an electrical control signal. Photonic processors designed using modulatable detector-based multipliers are significantly more compact than other types of photonic processors.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: November 9, 2021
    Assignee: Lightmatter, Inc.
    Inventors: Nicholas C. Harris, Darius Bunandar, Michael Gould, Carl Ramey, Shashank Gupta, Carlos Dorta-Quinones
  • Publication number: 20210333818
    Abstract: Photonic processors are described. The photonic processors described herein are configured to perform matrix multiplications (e.g., matrix vector multiplications). Matrix multiplications are broken down in scalar multiplications and scalar additions. Some embodiments relate to devices for performing scalar additions in the optical domain. One optical adder, for example, includes an interferometer having a plurality of phase shifters and a coherent detector. Leveraging the high-speed characteristics of these optical adders, some processors are sufficiently fast to support clocks in the tens of gigahertz of frequency, which represent a significant improvement over conventional electronic processors.
    Type: Application
    Filed: April 26, 2021
    Publication date: October 28, 2021
    Applicant: Lightmatter, Inc.
    Inventors: Nicholas C. Harris, Anthony Kopa, Carl Ramey, Darius Bunandar, Michael Gould
  • Publication number: 20210278590
    Abstract: Described herein are photonic communication platforms that can overcome the memory bottleneck problem, thereby enabling scaling of memory capacity and bandwidth well beyond what is possible with conventional computing systems. Some embodiments provide photonic communication platforms that involve use of photonic modules. Each photonic module includes programmable photonic circuits for placing the module in optical communication with other modules based on the needs of a particular application. The architecture developed by the inventors relies on the use of common photomask sets (or at least one common photomask) to fabricate multiple photonic modules in a single wafer. Photonic modules in multiple wafers can be linked together into a communication platform using optical or electronic means.
    Type: Application
    Filed: May 6, 2021
    Publication date: September 9, 2021
    Applicant: Lightmatter, Inc.
    Inventors: Nicholas C. Harris, Carl Ramey, Michael Gould, Thomas Graham, Darius Bunandar, Ryan Braid, Mykhailo Tymchenko
  • Patent number: 11093215
    Abstract: Photonic processors are described. The photonic processors described herein are configured to perform matrix-matrix (e.g., matrix-vector) multiplication. Some embodiments relate to photonic processors arranged according to a dual-rail architecture, in which numeric values are encoded in the difference between a pair optical signals (e.g., in the difference between the powers of the optical signals). Relative to other architectures, these photonic processors exhibit increased immunity to noise. Some embodiments relate to photonic processors including modulatable detector-based multipliers. Modulatable detectors are detectors designed so that the photocurrent can be modulated according to an electrical control signal. Photonic processors designed using modulatable detector-based multipliers are significantly more compact than other types of photonic processors.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: August 17, 2021
    Assignee: Lightmatter, Inc.
    Inventors: Nicholas C. Harris, Darius Bunandar, Michael Gould, Carl Ramey, Shashank Gupta, Carlos Dorta-Quinones
  • Publication number: 20210242124
    Abstract: Described herein are photonic communication platforms and related packages. In one example, a photonic package includes a substrate carrier having a recess formed through the top surface of the substrate carrier. The substrate carrier may be made of a ceramic laminate. A photonic substrate including a plurality of photonic modules is disposed in the recess. The photonic modules may be patterned using a common photomask, and as a result, may share a same layer pattern. A plurality of electronic dies may be positioned on top of respective photonic modules. The photonic modules enable communication among the dies in the optical domain. Power delivery substrates may be used to convey electric power from the substrate carrier to the electronic dies and to the photonic substrate. Power delivery substrates may be implemented, for example, using bridge dies or interposers (e.g., silicon or organic interposers).
    Type: Application
    Filed: February 2, 2021
    Publication date: August 5, 2021
    Applicant: Lightmatter, Inc.
    Inventors: Sukeshwar Kannan, Carl Ramey, Jon Elmhurst, Darius Bunandar, Nicholas C. Harris
  • Publication number: 20210224454
    Abstract: Aspects relate to a photonic processing system, an integrated circuit, and a method of operating an integrated circuit to control components to modulate optical signals. A photonic processing system, comprising: a photonic integrated circuit comprising: a first electrically-controllable photonic component electrically coupling an input pin to a first output pin; and a second electrically-controllable photonic component electrically coupling the input pin to a second output pin.
    Type: Application
    Filed: January 14, 2021
    Publication date: July 22, 2021
    Applicant: Lightmatter, Inc.
    Inventors: Carl Ramey, Darius Bunandar, Nicholas C. Harris
  • Patent number: 11036002
    Abstract: Described herein are photonic communication platforms that can overcome the memory bottleneck problem, thereby enabling scaling of memory capacity and bandwidth well beyond what is possible with conventional computing systems. Some embodiments provide photonic communication platforms that involve use of photonic modules. Each photonic module includes programmable photonic circuits for placing the module in optical communication with other modules based on the needs of a particular application. The architecture developed by the inventors relies on the use of common photomask sets (or at least one common photomask) to fabricate multiple photonic modules in a single wafer. Photonic modules in multiple wafers can be linked together into a communication platform using optical or electronic means.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: June 15, 2021
    Assignee: Lightmatter, Inc.
    Inventors: Nicholas C. Harris, Carl Ramey, Michael Gould, Thomas Graham, Darius Bunandar, Ryan Braid, Mykhailo Tymchenko
  • Publication number: 20210157547
    Abstract: Photonic processors are described. The photonic processors described herein are configured to perform matrix-matrix (e.g., matrix-vector) multiplication. Some embodiments relate to photonic processors arranged according to a dual-rail architecture, in which numeric values are encoded in the difference between a pair optical signals (e.g., in the difference between the powers of the optical signals). Relative to other architectures, these photonic processors exhibit increased immunity to noise. Some embodiments relate to photonic processors including modulatable detector-based multipliers. Modulatable detectors are detectors designed so that the photocurrent can be modulated according to an electrical control signal. Photonic processors designed using modulatable detector-based multipliers are significantly more compact than other types of photonic processors.
    Type: Application
    Filed: November 20, 2020
    Publication date: May 27, 2021
    Applicant: Lightmatter, Inc.
    Inventors: Darius Bunandar, Nicholas C. Harris, Michael Gould, Carl Ramey, Shashank Gupta, Carlos Dorta-Quinones
  • Publication number: 20210157878
    Abstract: Photonic processors are described. The photonic processors described herein are configured to perform matrix-matrix (e.g., matrix-vector) multiplication. Some embodiments relate to photonic processors arranged according to a dual-rail architecture, in which numeric values are encoded in the difference between a pair optical signals (e.g., in the difference between the powers of the optical signals). Relative to other architectures, these photonic processors exhibit increased immunity to noise. Some embodiments relate to photonic processors including modulatable detector-based multipliers. Modulatable detectors are detectors designed so that the photocurrent can be modulated according to an electrical control signal. Photonic processors designed using modulatable detector-based multipliers are significantly more compact than other types of photonic processors.
    Type: Application
    Filed: November 23, 2020
    Publication date: May 27, 2021
    Applicant: Lightmatter, Inc.
    Inventors: Darius Bunandar, Nicholas C. Harris, Michael Gould, Carl Ramey, Shashank Gupta, Carlos Dorta-Quinones
  • Publication number: 20210118853
    Abstract: A memory device is described. The memory device comprises a plurality of stacked memory layers, wherein each of the plurality of stacked memory layers comprises a plurality of memory cells. The memory device further comprises an optical die bonded to the plurality of stacked memory layers and in electrical communication with the stacked memory layers through one or more interconnects. The optical die comprises an optical transceiver, and a memory controller configured to control read and/or write operations of the stacked memory layers. The optical die may be positioned at one end of the plurality of stacked memory layers. The one or more interconnects may comprise one or more through silicon vias (TSV). The plurality of memory cells may comprise a plurality of solid state memory cells. The memory devices described herein can enable all-to-all, point-to-multipoint and ring architectures for connecting logic units with memory devices.
    Type: Application
    Filed: April 30, 2019
    Publication date: April 22, 2021
    Applicant: Lighmatter, Inc.
    Inventors: Nicholas C. Harris, Carl Ramey
  • Patent number: 10942876
    Abstract: One embodiment includes a computing device including peripheral component bus interfaces for connection to a peripheral component bus, a first integrated circuit (IC) chip comprising a processor to initiate a register setup process of the device, a second IC chip including a tile processor including multiple tiles, each tile including at least a processing core configured to generate requests to at least one of the peripheral component bus interfaces, steering configuration registers to store steering configuration data, and steering logic to steer the generated requests responsively to the steering configuration data in the steering configuration registers, and steering register setup circuitry including a multicaster and a register setup memory, wherein the processor is configured to write the steering configuration data to the register setup memory, and the multicaster is configured to multicast the steering configuration data written to the register setup memory to the steering configuration registers of
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: March 9, 2021
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Carl Ramey, Christopher Jackson, Diane Orf, Matt Orsini, Michael Cotsford, Mark B. Rosenbluth, Rui Xu