Patents by Inventor Carl V. Reynolds

Carl V. Reynolds has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6920689
    Abstract: A interconnect structure is inexpensively manufactured and easily insertable into a socket. The interconnect structure is manufactured by forming a sacrificial substrate with cavities that is covered by a masking material having openings corresponding to the cavities. A first plating process is performed by depositing conductive material, followed by coupling wires within the openings and performing another plating process by depositing more conductive material. The interconnect structure is completed by first removing the masking material and sacrificial substrate. Ends of the wires are coupled opposite now-formed contact structures to a board. To complete the socket, a support device is coupled to the board to hold a tested integrated circuit.
    Type: Grant
    Filed: December 6, 2002
    Date of Patent: July 26, 2005
    Assignee: FormFactor, Inc.
    Inventors: Igor Y. Khandros, Gaetan L. Mathieu, Carl V. Reynolds
  • Publication number: 20040113640
    Abstract: Methods and apparatuses for testing semiconductor devices are disclosed. Over travel stops limit over travel of a device to be tested with respect to probes of a probe card assembly. Feedback control techniques are employed to control relative movement of the device and the probe card assembly. A probe card assembly includes flexible base for absorbing excessive over travel of the device to be tested with respect to the probe card assembly.
    Type: Application
    Filed: December 16, 2002
    Publication date: June 17, 2004
    Inventors: Timothy E. Cooper, Benjamin N. Eldridge, Carl V. Reynolds, Ravindra Vaman Shenoy
  • Publication number: 20040107568
    Abstract: A interconnect structure is inexpensively manufactured and easily insertable into a socket. The interconnect structure is manufactured by forming a sacrificial substrate with cavities that is covered by a masking material having openings corresponding to the cavities. A first plating process is performed by depositing conductive material, followed by coupling wires within the openings and performing another plating process by depositing more conductive material. The interconnect structure is completed by first removing the masking material and sacrificial substrate. Ends of the wires are coupled opposite now-formed contact structures to a board. To complete the socket, a support device is coupled to the board to hold a tested integrated circuit.
    Type: Application
    Filed: December 6, 2002
    Publication date: June 10, 2004
    Applicant: FormFactor, Inc.
    Inventors: Igor Y. Khandros, Gaetan L. Mathieu, Carl V. Reynolds
  • Publication number: 20040016119
    Abstract: A method of making a microelectronic spring contact array comprises forming a plurality of spring contacts on a sacrificial substrate and then releasing the spring contacts from the sacrificial substrate. Each of the spring contacts has an elongated beam having a base end. The method of making the array includes attaching the spring contacts at their base ends to a base substrate after they have been released entirely from the sacrificial substrate, so that each contact extends from the base substrate to a distal end of its beams. The distal ends are aligned with a predetermined array of tip positions. In an embodiment of the invention, the spring contacts are formed by patterning contours of the spring contacts in a sacrificial layer on the sacrificial substrate. The walls of patterned recesses in the sacrificial layer define side profiles of the spring contacts, and a conductive material is deposited in the recesses to form the elongated beams of the spring contacts.
    Type: Application
    Filed: July 24, 2002
    Publication date: January 29, 2004
    Applicant: FormFactor, Inc.
    Inventors: Benjamin N. Eldridge, Gaetan L. Mathieu, Carl V. Reynolds
  • Publication number: 20030112001
    Abstract: The present invention discloses a cover over electrical contacts of a probe card used in testing die on a wafer. A testing machine is disclosed as having the covered probe card therein. Various mechanisms for uncovering the electrical contacts while it is located in the tester machine are disclosed.
    Type: Application
    Filed: December 19, 2001
    Publication date: June 19, 2003
    Inventors: Benjamin N. Eldridge, Carl V. Reynolds
  • Publication number: 20020132501
    Abstract: Double-sided interposer assemblies and methods for forming and using them. In one example of the invention, an interposer comprises a substrate having a first surface and a second surface opposite of said first surface, a first plurality of contact elements disposed on said first side of said substrate, and a second plurality of contact elements disposed on said second surface of said substrate, wherein said interposer connects electronic devices via said first and said second plurality of contact elements.
    Type: Application
    Filed: March 16, 2001
    Publication date: September 19, 2002
    Inventors: Benjamin N. Eldridge, Carl V. Reynolds
  • Patent number: 6090237
    Abstract: Resin overflow in the interior cavity of a multilayer substrate assembly during lamination is restricted and controlled by a plug inserted into the cavity prior to bonding. The plug is shaped to mate with the stepped vertical profile of the cavity. The plug may include sections of materials of different hardness to support the stepped vertical profile of the plug and to facilitate removal of the plug after lamination. The plug may also include textured surfaces to facilitate removal of the plug. Pressurized gas is introduced at the interface between the plug and the cavity surface to dislodge the plug and a vacuum may be applied to the top of the plug to facilitate removal. The cavity may also be coated with layer of photo sensitive material to protect the metal bonding surfaces in the cavity from damage by the plug and to prevent particulate contamination during lamination.
    Type: Grant
    Filed: January 26, 1998
    Date of Patent: July 18, 2000
    Inventors: Carl V. Reynolds, Alex M. Neussendorfer, Jeffrey K. Kennedy