Patents by Inventor Carlos A. Mazure

Carlos A. Mazure has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9496877
    Abstract: The invention relates to a circuit including a transistor of a first type of channel in series with a transistor of a second type of channel between first and second terminals for applying a power supply potential, each of the transistors being a multiple gate transistor having at least a first (G1P, G1N) and a second (G2P, G2N) independent control gates, characterized in that at least one of the transistors is configured for operating in a depletion mode under the action of a second gate signal applied to its second control gate (G2p, G2N).
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: November 15, 2016
    Assignee: Soitec
    Inventors: Carlos Mazure, Richard Ferrant, Bich-Yen Nguyen
  • Patent number: 9490264
    Abstract: The invention relates to a semiconductor device produced on a semiconductor-on-insulator substrate that includes a thin layer of semiconductor material separated from a base substrate by a buried insulating layer, the device including a first conducting region in the thin layer, a second conducting region in the base substrate and a contact connecting the first region to the second region through the insulating layer. The invention also relates to a process for fabricating such semiconductor devices.
    Type: Grant
    Filed: January 4, 2011
    Date of Patent: November 8, 2016
    Assignee: Soitec
    Inventors: Carlos Mazure, Richard Ferrant
  • Publication number: 20160020326
    Abstract: The present invention relates to a double-gate finFET comprising: at least two fins (FIN) realizing a single channel; a back-gate (BG) placed between the fins; and a front-gate (FG), placed outside of the fins. Further, the invention relates to a manufacturing process, resulting in the double-gate finFET.
    Type: Application
    Filed: March 13, 2014
    Publication date: January 21, 2016
    Inventors: Carlos MAZURE, Franz HOFMANN
  • Patent number: 9159400
    Abstract: A semiconductor memory having bit lines and wordlines crossing each other, a memory cell array formed by memory cells arranged in rows and columns on crossover points of the bit lines and wordlines, and sense amplifier banks arranged on opposite sides of the memory cell array. Each sense amplifier bank has staggered sense amplifiers connected to a bit line according to an interleaved arrangement whereby bit lines alternate in the direction of the wordlines between bit lines coupled to different sense amplifiers. This results in interconnect spaces parallel to the bit lines. Also, each sense amplifier bank includes a local column decoder for selecting a sense amplifier and which is staggered with the sense amplifiers and coupled to the sense amplifier by an output line running in an available interconnect space parallel to the bit lines.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: October 13, 2015
    Assignee: Soitec
    Inventors: Richard Ferrant, Gerhard Enders, Carlos Mazure
  • Publication number: 20150145049
    Abstract: The present invention relates to a floating body memory cell comprising: a first MOS transistor and a second MOS transistor, wherein at least the second MOS transistor has a floating body; and wherein the first and second MOS transistors are configured such that charges can be moved to/from the floating body of the second MOS transistor via the first MOS transistor.
    Type: Application
    Filed: May 8, 2013
    Publication date: May 28, 2015
    Inventors: Franz Hoffman, Richard Ferrant, Carlos Mazure
  • Patent number: 9035474
    Abstract: The invention relates to a method for manufacturing a semiconductor substrate, in particular, a semiconductor-on-insulator substrate by providing a donor substrate and a handle substrate, forming a pattern of one or more doped regions typically inside the handle substrate, and then attaching such as by molecular bonding the donor substrate and the handle substrate to obtain a donor-handle compound.
    Type: Grant
    Filed: June 3, 2010
    Date of Patent: May 19, 2015
    Assignee: Soitec
    Inventors: Carlos Mazure, Richard Ferrant, Konstantin Bourdelle, Bich-Yen Nguyen
  • Patent number: 8987114
    Abstract: Methods of forming semiconductor structures include transferring a portion (116a) of a donor structure to a processed semiconductor structure (102) that includes at least one non-planar surface. An amorphous film (144) may be formed over at least one non-planar surface of the bonded semiconductor structure, and the amorphous film may be planarized to form one or more planarized surfaces. Semiconductor structures include a bonded semiconductor structure having at least one non-planar surface, and an amorphous film disposed over the at least one non-planar surface. The bonded semiconductor structure may include a processed semiconductor structure and a portion of a single crystal donor structure attached to a non-planar surface of the processed semiconductor structure.
    Type: Grant
    Filed: February 22, 2011
    Date of Patent: March 24, 2015
    Assignee: SOITEC
    Inventors: Carlos Mazure, Bich-Yen Nguyen, Mariam Sadaka
  • Publication number: 20140225648
    Abstract: The invention relates to a a circuit including a transistor of a first type of channel in series with a transistor of a second type of channel between first and second terminals for applying a power supply potential, each of the transistors being a multiple gate transistor having at least a first (G1P, G1N) and a second (G2P, G2N) independent control gates, characterized in that at least one of the transistors is configured for operating in a depletion mode under the action of a second gate signal applied to its second control gate (G2p, G2N).
    Type: Application
    Filed: September 30, 2011
    Publication date: August 14, 2014
    Applicant: SOITEC
    Inventors: Carlos Mazure, Richard Ferrant, Bich-Yen Nguyen
  • Publication number: 20140225182
    Abstract: A substrate comprises a base wafer, an insulating layer over the base wafer, and a top semiconductor layer over the insulating layer on a side thereof opposite the base wafer. The insulating layer comprises a charge-confining layer confined on one or both sides with diffusion barrier layers, wherein the charge-confining layer has a density of charges in absolute value higher than 1010 charges/cm2. Alternatively, the insulating layer comprises charge-trapping islands embedded therein, wherein the charge-trapping islands have a total density of charges in absolute value higher than 1010 charges/cm2.
    Type: Application
    Filed: April 15, 2014
    Publication date: August 14, 2014
    Applicant: Soitec
    Inventors: Mohamad A. Shaheen, Frederic Allibert, Gweltaz Gaudin, Fabrice Lallement, Didier Landru, Karine Landry, Carlos Mazure
  • Patent number: 8735946
    Abstract: Embodiments of the invention relate to substrates comprising a base wafer, an insulating layer and a top semiconductor layer, wherein the insulating layer comprises at least a zone wherein a density of charges is in absolute value higher than 1010 charges/cm2. The invention also relates to processes for making such substrates.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: May 27, 2014
    Assignee: Soitec
    Inventors: Mohamad A Shaheen, Frederic Allibert, Gweltaz Gaudin, Fabrice Lallement, Didier Landru, Karine Landry, Carlos Mazure
  • Patent number: 8664712
    Abstract: The invention relates to a flash memory cell having a FET transistor with a floating gate on a semiconductor-on-insulator (SOI) substrate composed of a thin film of semiconductor material separated from a base substrate by an insulating buried oxide (BOX) layer, The transistor has in the thin film, a channel, with two control gates, a front control gate located above the floating gate and separated from it by an inter-gate dielectric, and a back control gate located within the base substrate directly under the insulating (BOX) layer and separated from the channel by only the insulating (BOX) layer. The two control gates are designed to be used in combination to perform a cell programming operation. The invention also relates to a memory array made up of a plurality of memory cells according to the first aspect of the invention, which can be in an array of rows and columns, and a method of fabricating such memory cells and memory arrays.
    Type: Grant
    Filed: November 15, 2010
    Date of Patent: March 4, 2014
    Assignee: Soitec
    Inventors: Carlos Mazure, Richard Ferrant
  • Patent number: 8654602
    Abstract: A circuit made on a semiconductor-on-insulator substrate. The circuit includes a first transistor having a first channel, a second transistor having a second channel, with the transistors provided in serial association between first and second terminals for applying a power supply potential, each of the transistors comprising a drain region and a source region in the thin layer, a channel extending between the source region and the drain region, and a front control gate located above the channel. Each transistor has a back control gate formed in the base substrate below the channel of the transistor and capable of being biased in order to modulate the threshold voltage of the transistor. At least one of the transistors is configured for operating in a depletion mode under the action of a back gate signal which will sufficiently modulate its threshold voltage.
    Type: Grant
    Filed: June 13, 2012
    Date of Patent: February 18, 2014
    Assignee: Soitec
    Inventors: Carlos Mazure, Richard Ferrant, Bich-Yen Nguyen
  • Patent number: 8652887
    Abstract: The present invention relates to a method for providing a Silicon-On-Insulator (SOI) stack that includes a substrate layer, a first oxide layer on the substrate layer and a silicon layer on the first oxide layer (BOX layer). The method includes providing at least one first region of the SOI stack wherein the silicon layer is thinned by thermally oxidizing a part of the silicon layer and providing at least one second region of the SOI stack wherein the first oxide layer (BOX layer) is thinned by annealing.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: February 18, 2014
    Assignee: Soitec
    Inventors: Bich-Yen Nguyen, Carlos Mazure, Richard Ferrant
  • Publication number: 20140015023
    Abstract: Embodiments of the invention relate to substrates comprising a base wafer, an insulating layer and a top semiconductor layer, wherein the insulating layer comprises at least a zone wherein a density of charges is in absolute value higher than 1010 charges/cm2. The invention also relates to processes for making such substrates.
    Type: Application
    Filed: September 16, 2013
    Publication date: January 16, 2014
    Applicant: Soitec
    Inventors: Frederic Allibert, Gweltaz Gaudin, Fabrice Lallement, Didier Landru, Karine Landry, Carlos Mazure, Mohamad A. Shaheen
  • Patent number: 8625374
    Abstract: A sense amplifier for a series of cells of a memory, including a writing stage comprising a CMOS inverter, the input of which is directly or indirectly connected to an input terminal of the sense amplifier, and the output of which is connected to an output terminal of the sense amplifier intended to be connected to a local bitline addressing the cells of the series, and a reading stage that includes a sense transistor, the gate of which is connected to the output of the inverter and the drain of which is connected to the input of the inverter.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: January 7, 2014
    Assignee: Soitec
    Inventors: Carlos Mazure, Richard Ferrant, Bich-Yen Nguyen
  • Patent number: 8603896
    Abstract: A method for transferring a monocrystalline semiconductor layer onto a support substrate by implanting species in a donor substrate; bonding the donor substrate to the support substrate; and fracturing the donor substrate to transfer the layer onto the support substrate; wherein a portion of the monocrystalline layer to be transferred is rendered amorphous, without disorganizing the crystal lattice of a second portion of the layer, with the portions being, respectively, a surface portion and a buried portion of the monocrystalline layer; and wherein the amorphous portion is recrystallized at a temperature below 500° C., with the crystal lattice of the second portion serving as a seed for recrystallization.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: December 10, 2013
    Assignee: Soitec
    Inventors: Gweltaz Gaudin, Carlos Mazure
  • Patent number: 8575697
    Abstract: An SRAM-type memory cell that includes a semiconductor on insulator substrate having a thin film of semiconductor material separated from a base substrate by an insulating layer; and six transistors such as two access transistors, two conduction transistors and two charge transistors arranged so as to form with the conduction transistors two back-coupled inverters. Each of the transistors has a back control gate formed in the base substrate below the channel and able to be biased in order to modulate the threshold voltage of the transistor, with a first back gate line connecting the back control gates of the access transistors to a first potential and a second back gate line connecting the back control gates of the conduction transistors and charge transistors to a second potential. The first and second potentials can be modulated according to the type of cell control operation.
    Type: Grant
    Filed: March 2, 2011
    Date of Patent: November 5, 2013
    Assignee: Soitec
    Inventors: Carlos Mazure, Richard Ferrant, Bich-Yen Nguyen
  • Patent number: 8535996
    Abstract: Embodiments of the invention relate to substrates comprising a base wafer, an insulating layer and a top semiconductor layer, wherein the insulating layer comprises at least a zone wherein a density of charges is in absolute value higher than 1010 charges/cm2. The invention also relates to processes for making such substrates.
    Type: Grant
    Filed: March 13, 2008
    Date of Patent: September 17, 2013
    Assignee: SOITEC
    Inventors: Mohamad Shaheen, Frederic Allibert, Gweltaz Gaudin, Fabrice Lallement, Didier Landru, Karin Landry, Carlos Mazure
  • Patent number: 8508289
    Abstract: This invention provides a semiconductor device structure formed on a conventional semiconductor-on-insulator (SeOI) substrate defined by a pattern defining at least one field-effect transistor having: in the thin film of the SeOI substrate, a source region, a drain region, a channel region, and a front control gate region formed above the channel region; and in the base substrate beneath the buried oxide of the SeOI substrate, a back control gate region, arranged under the channel region and configured to shift the threshold voltage of the transistor in response to bias voltages. This invention also provides patterns defining standard-cell-type circuit structures and data-path-cell type circuit structures that include arrays of the FET patterns provided by this invention. Such circuit structures also include back gate lines connecting the back gate control regions. This invention also provides methods of operating and designing such semiconductor device structures.
    Type: Grant
    Filed: January 25, 2011
    Date of Patent: August 13, 2013
    Assignee: Soitec
    Inventors: Carlos Mazure, Richard Ferrant
  • Patent number: 8492844
    Abstract: The present invention relates to a method for the manufacture of a semiconductor device by providing a first substrate; providing a doped layer in a surface region of the first substrate; providing a buried oxide layer on the doped layer; providing a semiconductor layer on the buried oxide layer to obtain a semiconductor-on-insulator (SeOI) wafer; removing the buried oxide layer and the semiconductor layer from a first region of the SeOI wafer while maintaining the buried oxide layer and the semiconductor layer in a second region of the SeOI water; providing an upper transistor in the second region by forming a back gate in or by the doped layer; and providing a lower transistor in the first region by forming source and drain regions in or by the doped layer.
    Type: Grant
    Filed: November 28, 2011
    Date of Patent: July 23, 2013
    Assignee: Soitec
    Inventors: Gerhard Enders, Wolfgang Hoenlein, Franz Hofmann, Carlos Mazure