Abstract: A method for forming a transistor and a capacitor to provide, in one form, a DRAM cell (10). The capacitor of cell (10) is formed within a substrate (12). The capacitor has a first capacitor electrode (16) and a second capacitor electrode (20). A dielectric layer (18) is formed as an inter-electrode capacitor dielectric. A first transistor current electrode (36) is formed overlying and electrically connected to the first capacitor electrode (16). A channel region (38) is formed overlying the first transistor current electrode (36). A second transistor current electrode (40) is formed overlying the channel region (38). A conductive layer (30) is formed laterally adjacent the channel region (38) and isolated from the substrate (12) by dielectric layers (22 and 28). A conductive layer (30) functions as a gate electrode for the transistor and a sidewall dielectric (34) functions as a gate dielectric.

Abstract: A transistor is formed as either a bipolar transistor (10) or an MOS transistor (11). Each transistor (10 or 11) has a substrate (12). Bipolar transistor (10) has a first current electrode (26) underlying a control electrode (28), and a second current electrode (32) overlying the control electrode (28). MOS transistor (11) has a first current electrode (54) underlying a channel region (56), and a source lightly doped region (58) and a source heavily doped region (60) overlying the channel region (56). A control electrode conductive layer (40) is laterally adjacent a sidewall dielectric layer (48), and sidewall dielectric layer (48) is laterally adjacent channel region (56). Conductive layer (40) functions as a gate electrode for transistor (11). Each of the transistors (10 and 11) is vertically integrated such as in a vertically integrated BiMOS circuit. Transistors (10 and 11) can be electrically isolated by isolation ( 64 and 66).

Abstract: A contact is formed in a semiconductor device (10), independent of underlying topography or pitch. In one method of the present invention, an insulating layer (18) is deposited over a semiconductor substrate (12). An etch stop layer (20) is deposited over the insulating layer. A frame structure (22) is formed on the etch stop material and defines at least one contact region (23 and/or 25) within which the etch stop material is exposed. The exposed portions of the etch stop material are removed from the contact region to expose a portion of the insulating layer. The exposed portion of the insulating layer is then anisotropically etched and at least one contact (30 and/or 32) is formed in the contact region. Depending on where the contact region is positioned, either a self-aligned contact or a non-self-aligned contact may be formed, or both types of contacts may be formed simultaneously.

Abstract: A method for forming a grown bipolar transistor electrode contact wherein a substrate (12) is provided. A doped region (31) is formed within the substrate (12). A dielectric layer (26) is formed having an opening (36) which exposes a portion of the doped region (31). Conductive spacers (38) are formed adjacent a sidewall of the dielectric layer (26). A conductive region (34) is formed through either a selective process or an epitaxial process by using the conductive spacers (38) as a source for epitaxial or selective formation. The conductive region (34) forms the grown bipolar electrode contact by electrically contacting the doped region (31). The conductive region (34) is optionally overgrown in a lateral direction over a top surface of the dielectric layer (26) to form a self-aligned electrical contact pad for the doped region (31).

Abstract: A semiconductor device and process wherein an ITLDD device (60) is formed having an inverse-T (IT) transistor gate with a variable work function (.PHI.) across the gate. The variable work function is attained by depositing a work function adjusting layer onto the thin gate extensions of the IT-gate. In accordance with one embodiment of the invention, a semiconductor substrate (10) of a first conductivity type is provided having a gate dielectric layer (12) formed thereon. First and second lightly doped regions (36, 37) of a second conductivity type are formed in the substrate which are spaced apart by a channel region (38). An IT-gate electrode (48) is formed on the gate dielectric layer overlying the first and second lightly doped regions and the channel region. The IT-gate has a relatively thick central section (32) and relatively thin lateral extensions (50) projecting from the central portion along the gate dielectric layer.

Abstract: A vertical bipolar transistor (10) and a lateral bipolar transistor (11) are formed wherein both transistors (10 and 11) have a substrate (12). A dielectric layer (22) is formed overlying the substrate (12), and a conductive layer (24) is formed overlying the dielectric layer (22). Another dielectric layer (26) is formed overlying the conductive layer (24). A device opening is formed through the dielectric layers (22 and 26) and the conductive layer (24). A conductive region (33) is formed within the device opening and overlying the substrate (12). For transistor (10), the conductive region (33) is doped to form an active base electrode region (36) and a first current electrode region (38). A second current electrode region is formed via a diffusion (16). For transistor (11), a base electrode is formed via a diffused base region (46), and first and second current electrodes are respectively formed via diffused regions (44 and 48).

Abstract: A semiconductor device and process wherein an ITLDD device (60) is formed having an inverse-T (IT) transistor gate with a variable work function (.PHI.) across the gate. The variable work function is attained by depositing a work function adjusting layer onto the thin gate extensions of the IT-gate. In accordance with one embodiment of the invention, a semiconductor substrate (10) of a first conductivity type is provided having a gate dielectric layer (12) formed thereon. First and second lightly doped regions (36, 37) of a second conductivity type are formed in the substrate which are spaced apart by a channel region (38). An IT-gate electrode (48) is formed on the gate dielectric layer overlying the first and second lightly doped regions and the channel region. The IT-gate has a relatively thick central section (32) and relatively thin lateral extensions (50) projecting from the central portion along the gate dielectric layer.