Abstract: A continuous contact hole is formed in an insulation layer that separates a storage capacitor from a switching transistor. All except a section of the contact hole is filled with poly-Si. A conductive, oxidizable interlayer and a conductive oxygen barrier layer are deposited on the Poly-Si in the remaining section of the contact hole such that the interlayer is completely surrounded by the poly-Si of the contact hole, the insulation layer, and the barrier layer.

Abstract: A storage capacitor, in particular a ferroelectric or paraelectric storage capacitor, and an associated contact-making structure are formed in such a way that the storage capacitor has a first electrode layer, a second electrode layer and a dielectric, ferroelectric or paraelectric capacitor intermediate layer. Proceeding from the plane of the surface of the insulation layer, the storage capacitor extends at least partly into the interior of the via contact and is electrically connected to the via contact.

Abstract: A semiconductor memory configuration has a plurality of selection transistors. Each selection transistor is connected to a first electrode of a storage capacitor. A second electrode of the storage capacitor is connected to a common plate. The common plate is provided below the selection transistors in a semiconductor body. A method of fabricating a semiconductor memory configuration is also provided.

Abstract: A process for producing an integrated semiconductor memory configuration, in particular one suited to the use of ferroelectric materials as storage dielectrics, in which a conductive connection between one electrode of a storage capacitor and a selection transistor is not produced until after the storage dielectric has been deposited; and a semiconductor memory configuration produced using the production process.

Abstract: In a method for fabricating a high-epsilon dielectric/ferroelectric capacitor, a patterning layer with a central base layer zone and a Si-filled trench laterally surrounding the latter is produced. Above that, a metal layer is deposited and is silicided above the Si-filled trench. Through oxidation of the silicided metal layer section the latter migrates into the trench and a base electrode is formed above the base layer zone.

Abstract: Disclosed is a method for producing semiconductor elements including a metal layer (10) configured on a semiconductor substrate (5). The inventive method consists of the following steps: a silicon layer (15) is deposited on a metal layer (10); an etch mask is applied in order to structure the silicon layer (1%); the silicon layer is selectively etched (15) using the etch mask (25); and the metal layer (10) is structured in an etching process using a selectively etched silicon layer (15) as a hard mask.

Abstract: A continuous contact hole is formed in an insulation layer that separates a storage capacitor from a switching transistor. All except a section of the contact hole is filled with poly-Si. A conductive, oxidizable interlayer and a conductive oxygen barrier layer are deposited on the Poly-Si in the remaining section of the contact hole such that the interlayer is completely surrounded by the poly-Si of the contact hole, the insulation layer, and the barrier layer.

Abstract: A circuit includes a sensor delivering a charge, a capacitor non-volatilely storing the charge, and a read and reset circuit reading out the stored charge. The capacitor has further connection terminals connected to the read and reset circuit and in parallel with the sensor terminals, and a ferroelectric storage dielectric intermittently connected to the sensor. The sensor can be a photodiode, a phototransistor, a Hall sensor, or a thermoelement. A switch can be connected between one of the further terminals and one of the sensor terminals. Preferably, the switch is a transistor and a drive circuit drives it. The sensor and the capacitor are formed in a semiconductor body. During a storage procedure, time periods during which the switch is on are coordinated with the sensor and/or capacitor to keep an electrical field present between the further terminals below a maximum value at which the ferroelectric dielectric saturates.

Abstract: A storage capacitor, in particular a ferroelectric or paraelectric storage capacitor, and an associated contact-making structure are formed in such a way that the storage capacitor has a first electrode layer, a second electrode layer and a dielectric, ferroelectric or paraelectric capacitor intermediate layer. Proceeding from the plane of the surface of the insulation layer, the storage capacitor extends at least partly into the interior of the via contact and is electrically connected to the via contact.

Abstract: In a method for fabricating a high-epsilon dielectric/ferroelectric capacitor, a patterning layer with a central base layer zone and a Si-filled trench laterally surrounding the latter is produced. Above that, a metal layer is deposited and is silicided above the Si-filled trench. Through oxidation of the silicided metal layer section the latter migrates into the trench and a base electrode is formed above the base layer zone.

Abstract: A microelectronic structure is described which contains a first conductive layer for preventing oxygen diffusion at the structure. The first conductive layer contains a base material and at least one oxygen-binding admixture that is provided with at least one element from the fourth subgroup or the lanthane group. In a preferred embodiment, the microelectronic structure is used in semiconductor storage components with a metal oxide dielectric as a condenser dielectric.

Abstract: A layer configuration includes a material layer and a diffusion barrier which blocks diffusing material components. The barrier is disposed in the vicinity of a layer boundary of the material layer and is formed predominantly in grain boundaries of the material layer. A process for producing a diffusion barrier is also provided.

Abstract: The method deals with plasma-structuring by etching, in particular with the plasma-structuring of materials at high temperatures. The application of a chemical etching process at high temperatures is made possible by the prior deposition of a polyimide mask.

Abstract: The integrated semiconductor memory configuration has a semiconductor body in which selection transistors and storage capacitors are integrated. The storage capacitors have a dielectric layer configured between two electrodes. At least the upper electrode is constructed in a layered manner with a platinum layer, that is seated on the dielectric layer, and a thicker, base metal layer lying above the platinum layer.

Abstract: Process for producing an integrated semiconductor memory configuration, in particular one suited to the use of ferroelectric materials as storage dielectrics, in which a conductive connection between one electrode of a storage capacitor and a selection transistor is not produced until after the storage dielectric has been deposited; and a semiconductor memory configuration produced using the production process.

Abstract: Process for producing an integrated semiconductor memory configuration, in particular one suited to the use of ferroelectric materials as storage dielectrics, in which a conductive connection between one electrode of a storage capacitor and a selection transistor is not produced until after the storage dielectric has been deposited; and a semiconductor memory configuration produced using the production process.

Abstract: Disclosed is a method for producing semiconductor elements including a metal layer (10) configured on a semiconductor substrate (5). The inventive method consists of the following steps: a silicon layer (15) is deposited on a metal layer (10); an etch mask is applied in order to structure the silicon layer (1%); the silicon layer is selectively etched (15) using the etch mask (25); and the metal layer (10) is structured in an etching process using a selectively etched silicon layer (15) as a hard mask.

Abstract: A method for producing a memory configuration that comprises a multiplicity of memory cells, and has storage capacitors whose first electrodes are configured in plate form in a parallel manner one above the other. These electrodes are in electrical contact with selection transistors of the memory cell through contact plugs having different lengths. The first electrodes preferably extend beyond the cell area of one memory cell.

Abstract: A method for producing an integrated semiconductor memory configuration, in particular uses ferroelectric materials as storage dielectrics. A conductive connection between a first electrode of a storage capacitor and a selection transistor is produced only after deposition of the storage dielectric.

Abstract: A ceramic layer, in particular having ferroelectric, dielectric or superconducting properties, uses compounds with a simple structure as precursors and only methanoic acid, acetic acid or propionic acid and, where appropriate, water as solvent.