Abstract: A production process for a capacitor electrode formed of a platinum metal includes producing a conductive electrode body on a substrate having a silicon-containing surface for the capacitor electrode. Platinum is deposited over the full surface, the platinum is silicized in a temperature step outside the electrode body and the platinum silicide is removed. The advantage of the invention is the avoidance of an etching process for metallic platinum.

Abstract: A process for producing a ceramic layer containing Bi, in particular having ferroelectric, dielectric or superconducting properties, includes using only an organic acid C.sub.n H.sub.2n+1 COOH wherein n=0, 1 or 2 and, where appropriate, water, as a solvent for the precursor containing Bi.

Abstract: A barrier layer is formed on the contact plug of the semiconductor body. The barrier layer prevents oxidation of the contact plug. The barrier layer is produced by chemically reacting a prestructured metallic transition material with one or more reaction partners.

Abstract: A memory configuration with a self-aligning non-integrated capacitor configuration includes a capacitor configuration and a transistor configuration which can be joined together in a self-aligning manner in such a way that each first contact of a transistor of the transistor configuration is connected to a respective second contact of a memory capacitor of the capacitor configuration. In order to align the two configurations, the second contacts are constructed in a protruding manner, and when joining takes place they engage in a structure including elevations.

Abstract: An integrated memory includes a cell array having bit lines, word lines and writable memory cells. A first differential sense amplifier has connections connected to a data line pair through which the first sense amplifier reads information from one of the memory cells during a read access operation in order to amplify it subsequently, and through which the first sense amplifier writes information to one of the memory cells during a write access operation. The relevant information is transferred as differential signals through the data line pair and is temporarily stored by the first sense amplifier during every write access operation. The memory also has a switching unit through which the data line pair is connected to the connections of the first sense amplifier, for interchanging the lines of the data line pair in relation to the connections of the first sense amplifier, depending on the switching state of the switching unit.

Abstract: The invention relates to a semiconductor configuration for integrated circuits, in which a stacked cell has a contact hole filled with a plug in an insulating layer, a capacitor having a lower electrode, which faces the plug, a paraelectric or ferroelectric dielectric and an upper electrode being provided on the contact hole. A barrier layer is situated between the plug and the lower electrode and is surrounded by a silicon nitride collar, which reliably prevents oxidation of the barrier layer.

Abstract: A method for producing a noble metal-containing structure on a substrate, and a semiconductor component having such a noble metal-containing structure, include introducing a noble metal into a preliminary structure by converting a gaseous compound of the noble metal with a non-noble metal in a preliminary structure into elementary noble metal and a gaseous compound of the non-noble metal. The process continues until a desired amount of the non-noble metal in the preliminary structure is replaced by the noble metal.

Abstract: A raised basic structure is first made from a conducting or nonconducting, easily structurable substitute material. Electrode material, such as platinum, is then sputtered onto the basic structure. The layer thickness of the electrode material is greater on the surface and on the side walls of the basic structure than on the neighbouring surface. After a subsequent anisotropic etching process, the electrode material remains only on the basic structure, including the top surface and the side walls. The process is applicable to memory cells having a capacitor dielectric with a high-.epsilon.-dielectric or ferroelectric material.