Abstract: A circuit structure for a matrix of EEPROM memory cells, being of a type which comprises a matrix of cells including plural rows and columns, with each row being provided with a word line and a control gate line and each column having a bit line; the bit lines, moreover, are gathered into groups or bytes of simultaneously addressable adjacent lines. Each cell in the matrix incorporates a floating gate transistor which is coupled to a control gate, connected to the control gate line, and is connected serially to a selection transistor; also, the cells of each individual byte share their respective source areas, which areas are structurally independent for each byte and are led to a corresponding source addressing line extending along a matrix column.

Abstract: A method for producing electrically erasable and programmable read-only memory cells with a single polysilicon level, including the use of a sacrificial layer of silicon oxide to produce a high-thickness silicon oxide layer on the active area. The active area of the cell is protected from heavy source and drain implantation in order to improve reliability.

Abstract: A method for forming thin oxide portions in electrically erasable and programmable read-only memory cells, including the use of the enhanced oxidation effect and the lateral diffusion of heavy doping, for obtaining a tunnel portion whose dimensions are smaller than the resolution of the photolithographic method used.

Abstract: The process provides for the simultaneous N+ type implantation of areas of a semiconductor substrate of type P for the formation of a control gate and of highly doped regions of source and drain, defining a channel region. After oxide growth there is executed the deposition and the definition of a polysilicon layer, one region of which constitutes a floating gate above the control gate and the channel region and partially superimposed over the regions of source and drain.

Abstract: This invention provides bicyclic heterocyclic derivatives and their pharmaceutically acceptable salts useful for the treatment of hypertension, urethral and lower urinary tract contractions, and other disorders. The compounds are also useful for binding .alpha..sub.1 -adrenergic and 5HT.sub.1A serotonergic receptors, in vitro or in vivo.

Abstract: A compound of the general formula: ##STR1## wherein X represents --CO--, --COO--, --CONH--, --CON(CH.sub.3)--, --CH.sub.2 NH--, --CH.sub.2 N(CH.sub.3)--, --CH.sub.2 NHCO--, --CH.sub.2 N(CH.sub.3)CO--, --CH.sub.2 O--, --CH.sub.2 S--, --CH.sub.2 SO--, or --CH.sub.2 SO.sub.2 --; n represents an integer from 1 to 4; and B represents one of the following groups: ##STR2## wherein R.sub.1 represents a lower alkyl (C.sub.1 -C.sub.4) group; R.sub.2 represents a hydrogen atom or a lower alkyl (C.sub.1 -C.sub.4) group; R.sub.3 represents a hydrogen atom or OR.sub.4 group wherein R.sub.4 represents a lower alkyl (C.sub.1 -C.sub.4) group; p represents an integer from 1 to 3; and Y represents a valence bond (Y1), or one of the following groups: ##STR3## wherein R.sub.2 is as above defined as well as the enantiomers, diastereomers, N-oxides, prodrugs, metabolites, prodrugs of metabolites, and pharmaceutically acceptable salts of these compounds.

Abstract: The invention relates to benzopyranone and benzothiopyranone compounds, compositions and methods of use which have adrenergic and serotonergic activity.

Abstract: A method for forming thin oxide portions in electrically erasable and programmable read-only memory cells, including the use of the enhanced oxidation effect and the lateral diffusion of heavy doping, for obtaining a tunnel portion whose dimensions are smaller than the resolution of the photolithographic method used.

Abstract: A method for producing electrically erasable and programmable read-only memory cells with a single polysilicon level, including the use of a sacrificial layer of silicon oxide to produce a high-thickness silicon oxide layer on the active area. The active area of the cell is protected from heavy source and drain implantation in order to improve reliability.

Abstract: The manufacturing process comprises a first step of formation of an N type sink on a single-crystal silicon substrate, a second step of formation of an active area on the surface of said sink, a third step of implantation of N- dopant in a surface region of the sink inside said active area, a fourth step of growth of a layer of gate oxide over said region with N- dopant, a fifth step of N+ implantation inside said N- region, a sixth step of P+ implantation in a laterally displaced position with respect to said N+ region and a seventh step of formation of external contacts for said N+ and P+ regions. There is thus obtained a zener diode limiter, having a cut-off voltage which is stable over time and not much dependent on temperature and which does not require the addition of process steps with respect to those usually necessary for the accomplishment of EEPROM memory cells.

Abstract: The process provides for the simultaneous N+ type implantation of areas of a semiconductor substrate of type P for the formation of a control gate and of highly doped regions of source and drain, defining a channel region. After oxide growth there is executed the deposition and the definition of a polysilicon layer, one region of which constitutes a floating gate above the control gate and the channel region and partially superimposed over the regions of source and drain.

Abstract: A process for the optical resolution of racemic 1,4-dihydropyridines, containing isothioureido groups. Salification of racemic isothioureas with optically active acids produces diasteroisomeric mixtures of isothiouronium salts, that, using conventional techniques, are separated in the individual components to give optically pure isothioureides of 1,4-dihydropyridines and salts thereof with conventional acids. Said optically pure 1,4-dihydropyridines can then be subjected to desulphuration and to different transformations to give to other enantiomerically pure and therapeutically useful 1,4-dihydropyridines.

Abstract: A device for the rapid fastening and unfastening of a tubular filtering fabric, comprises:a) a bearing structure (1, 1', 1") able to support filtering fabric (7) in the form of the desired tubular section;b) a fastening sleeve (2, 2') placed at each end of the tubular filtering fabric (7) and working with an outside ring (3, 3') and an inserted annular seal (5, 5') to allow tight anchoring of each of the ends of the tubular filtering fabric; andc) a fastening head (4, 4') placed at each end of the filtering fabric (7) and working with the fastening sleeve (2, 2') to press the ring (3, 3') tight in a stable manner against the sleeve (2, 2').

Abstract: The process for manufacturing EEPROM memory cells having a single level of polysilicon and thin oxide with selection transistor, sensing transistor having a floating gate, control gate with a capacitive coupling to the floating gate and a tunnel area with thin oxide, comprises a first step involving the definition of active areas free of field oxide, a second step involving an ionic implantation at a coupling area between the control gate and the floating gate, a third step involving the creation of gate oxide at the active areas, a fourth step involving an additional ionic implantation at said coupling area between the control gate and the floating gate and at said tunnel area, a fifth step involving the removal of the gate oxide superimposed over said areas, a sixth step involving the differentiated growth of coupling oxide and tunnel oxide at said coupling areas and tunnel areas and a seventh step involving the deposition of a layer of polysilicon constituting the floating gate.

Abstract: An electrically erasable programmable read only memory (EEPROM) memory cell with 100% redundancy includes two tunnel storage elements (10, 18; 26, 30) which are connected in parallel between a common source voltage (16) and an enabling transistor (22) which is controlled by a transfer terminal (24) and leads to a bit line (14), with respective sensing transistors (12, 28) arranged in series with respect to the storage elements. According to the invention, the cell furthermore includes an auxiliary enabling transistor (40) which is arranged in series with the source and is controlled by the transfer terminal.

Abstract: The process call for N.sup.- doping of a predetermined portion of a type-P semiconductor substrate preceding deposit and definition of a layer of gate polysilicon on a part of said predetermined portion and on an adjacent portion of substrate. After oxidation of the polysilicon there is performed an N.sup.+ doping in the remaining part of said predetermined portion of the substrate and of an additional substrate portion located on the opposite side of the gate.

Abstract: A reference cell for reading EEPROM memory devices, capable of discharging any charges present in its own floating gate without varying the geometry of the cell with respect to that of the associated memory cells and without requiring specific manufacturing steps. For this purpose, a switch element, for example a diode, is provided between the floating gate and the substrate of the device and discharges any charges present in the floating gate toward the substrate during the cell idle state in the absence of read signals.

Abstract: Compounds of formula I ##STR1## wherein R.sub.1 is a cyano, nitro, benzoyl, acetyl, amido or alkoxycarbonyl group;R.sub.2 is substituted aryl- or heterocyclic residue;R.sub.3 is alkoxycarbonyl group;R.sub.4 and R.sub.5, being the same or different, are hydrogen, alkyl, aryl or heterocyclic groups;Y is oxygen, sulphur or substituted or unsubstituted nitrogen atom, that can be a part of a heterocyclic ring;n is 0, 1 or 2R6 and R.sub.10, that can be the same or different, are: hydrogen; C.sub.1 -C.sub.6 -alkyl optionally substituted by hydroxy, amino, monoalkyl and dialkylamino, C.sub.1 -C.sub.6 -alkoxy, C.sub.1 -C.sub.6 -alkoxycarbonyl, C.sub.1 -C.sub.3 -carbonyloxy, aryl, heteroaryl and cycloalkyl; a C.sub.1 -C.sub.12 -alkanoyl, aroyl or heteroaryl group optionally substituted by halogen, nitro, amino monoalkylamino, dialkylamino, hydroxy, C.sub.1 -C.sub.6 -alkoxy, C.sub.1 -C.sub.6 -alkoxycarbonyl, C.sub.1 -C.sub.6 -alkylthio, C.sub.1 -C.sub.3 -carbonyloxy, aryl, heteroaryl, cycloalkyl groups.

Abstract: A CMOS logic circuit for converting a low voltage logic signal with a range O-VCC into a high voltage logic signal with a range O-VPP, which may be entirely made with enhancement-type transistors, comprises an additional p-channel, decoupling transistor functionally connected in series with the p-channel transistor of the CMOS circuit which is connected to the high voltage node VPP and the additional decoupling transistor is driven by a bias voltage tied to the VPP voltage and lower than the latter by a certain preset value. The so-called gated breakdown of p-channel transistors is effectively prevented and furthermore these circuits, destined to operate under a high supply voltage, may be fabricated through a normal CMOS fabrication process not requiring particular fabrication techniques for the p-channel transistors subject to gated breakdown conditions or the formation of depletion-type transistors and without the use of special circuits which require oscillator generated driving signals.

Abstract: The cell is formed of a selection transistor, a detection transistor and a tunnel condenser. The detection Transistor has its own control gate formed with an n.sup.+ diffusion which is closed and isolated from those of the other cells of the same memory.