Abstract: Embodiments of the present invention provide systems, devices and methods for improving both the bandwidth of a BAW resonator bandpass filter and the suppression of out-of-band frequencies above the passband. In various embodiments of the invention, blocker inductors are located in series between the filter input and the filter output to realize both bandwidth enhancement and improved out-of-band frequency rejection. For example, a first blocker inductor may be located at the input and a second blocker inductor may be located at the output of a BAW resonator bandpass filter.

Abstract: Bonded wafer packages having first and second wafers bonded together forming a matrix of sealed devices, at least one of the wafers having a plurality of passive devices formed thereon, including at least one BAW resonator within each of the sealed devices, the first wafer having conductor filled through-holes forming electrical connections between the passive devices and connections assessable from outside the sealed devices, the bonded wafers being diced to form individual sealed devices. The devices may be duplexers, interstage filters or other circuits such as VCOs and RF circuits. Various embodiments are disclosed.

Abstract: A system, apparatus and method for providing filtering functionality and impedance transformation within a BAW resonator network are disclosed. In particular, a BAW resonator network is designed to provide bandpass capability and a transformation between its input impedance and output impedance. By effectively integrating impedance matching functionality within the BAW resonator network, discrete impedance matching elements previously required within a system may be removed or reduced in size. As a result, matching networks and their associated component costs, insertion losses, and board size contributions may be reduced. Harmonic termination may be provided within the BAW resonator network or a prematch stage to improve efficiency of a power amplifier.

Abstract: Embodiments of the present invention provide systems, devices and methods for improving both the bandwidth of a BAW resonator bandpass filter and the suppression of out-of-band frequencies above the passband. In various embodiments of the invention, blocker inductors are located in series between the filter input and the filter output to realize both bandwidth enhancement and improved out-of-band frequency rejection. For example, a first blocker inductor may be located at the input and a second blocker inductor may be located at the output of a BAW resonator bandpass filter.

Abstract: Embodiments of the present invention provide systems, devices and methods for improving both the bandwidth of a BAW resonator bandpass filter and the suppression of out-of-band frequencies above the passband. In various embodiments of the invention, blocker inductors are located in series between the filter input and the filter output to realize both bandwidth enhancement and improved out-of-band frequency rejection. For example, a first blocker inductor may be located at the input and a second blocker inductor may be located at the output of a BAW resonator bandpass filter.

Abstract: Bonded wafer packages having first and second wafers bonded together forming a matrix of sealed devices, at least one of the wafers having a plurality of passive devices formed thereon, including at least one BAW resonator within each of the sealed devices, the first wafer having conductor filled through-holes forming electrical connections between the passive devices and connections assessable from outside the sealed devices, the bonded wafers being diced to form individual sealed devices. The devices may be duplexers, interstage filters or other circuits such as VCOs and RF circuits. Various embodiments are disclosed.

Abstract: A system, apparatus and method for providing filtering functionality and impedance transformation within a BAW resonator network are disclosed. In particular, a BAW resonator network is designed to provide bandpass capability and a transformation between its input impedance and output impedance. By effectively integrating impedance matching functionality within the BAW resonator network, discrete impedance matching elements previously required within a system may be removed or reduced in size. As a result, matching networks and their associated component costs, insertion losses, and board size contributions may be reduced. Harmonic termination may be provided within the BAW resonator network or a prematch stage to improve efficiency of a power amplifier.

Abstract: A system, apparatus and method for providing filtering functionality and impedance transformation within a BAW resonator network are disclosed. In particular, a BAW resonator network is designed to provide band pass capability and a transformation between its input impedance and output impedance. By effectively integrating impedance matching functionality within the BAW resonator network, discrete impedance matching elements previously required within a system may be removed or reduced in size. As a result, matching networks and their associated component costs, insertion losses, and board size contributions may be reduced.

Abstract: A system, apparatus and method for providing filtering functionality and impedance transformation within a BAW resonator network are disclosed. In particular, a BAW resonator network is designed to provide bandpass capability and a transformation between its input impedance and output impedance. By effectively integrating impedance matching functionality within the BAW resonator network, discrete impedance matching elements previously required within a system may be removed or reduced in size. As a result, matching networks and their associated component costs, insertion losses, and board size contributions may be reduced. Harmonic termination may be provided within the BAW resonator network or a prematch stage to improve efficiency of a power amplifier.

Abstract: Embodiments of the present invention provide systems, devices and methods for improving both the bandwidth of a BAW resonator bandpass filter and the suppression of out-of-band frequencies above the passband. In various embodiments of the invention, blocker inductors are located in series between the filter input and the filter output to realize both bandwidth enhancement and improved out-of-band frequency rejection. For example, a first blocker inductor may be located at the input and a second blocker inductor may be located at the output of a BAW resonator bandpass filter.

Abstract: A system, apparatus and method for providing filtering functionality and impedance transformation within a BAW resonator network are disclosed. In particular, a BAW resonator network is designed to provide band pass capability and a transformation between its input impedance and output impedance. By effectively integrating impedance matching functionality within the BAW resonator network, discrete impedance matching elements previously required within a system may be removed or reduced in size. As a result, matching networks and their associated component costs, insertion losses, and board size contributions may be reduced.

Abstract: A system, apparatus and method for providing filtering functionality and impedance transformation within a BAW resonator network are disclosed. In particular, a BAW resonator network is designed to provide bandpass capability and a transformation between its input impedance and output impedance. By effectively integrating impedance matching functionality within the BAW resonator network, discrete impedance matching elements previously required within a system may be removed or reduced in size. As a result, matching networks and their associated component costs, insertion losses, and board size contributions may be reduced. Harmonic termination may be provided within the BAW resonator network or a prematch stage to improve efficiency of a power amplifier.

Abstract: Method and apparatus for power control in an RF amplifier having reduced noise and moderate gain slope. In one embodiment, a multistage RF amplifier includes a first stage having a transconductance amplifier with an output coupled to a variable gain amplifier, with the gain control including control of the collector-emitter voltage of the output transistor of the variable gain amplifier. In another embodiment, the variable gain amplifier is replaced with a single transistor, with the gain control including control of the collector-emitter voltage of the single transistor. Reduction of the collector-emitter voltage followed by a reduction in the base-emitter voltage of the second stage for reduced gain of the amplifier reduces noise in the amplifier output for reduced gains, typically providing a monotonically decreasing noise with gain reduction.

Abstract: A single bias block for a single or multiple low voltage RF circuits including one or more amplifiers and one or more single or double balanced mixers with compensation for temperature and integrated circuit process parameters. The power supply may be a lower voltage without sacrificing the dynamic range of the amplifier and/or mixer by applying full power supply voltage to the load with the bias applied to the base circuit through an operational amplifier and/or buffer circuit. For the mixer, a lower noise figure may also be realized by moving the gain control impedance from the emitter to the collector circuit. The circuits may be discrete components or part of an integrated circuit. Methods are disclosed for reducing the power supply voltage without affecting the dynamic range of an amplifier, for temperature and process parameter compensation, and for controlling the gain of a mixer without affecting input or output impedance.

Abstract: A single bias block for a single or multiple low voltage RF circuits including one or more amplifiers and one or more single or double balanced mixers with compensation for temperature and integrated circuit process parameters. The power supply may be a lower voltage without sacrificing the dynamic range of the amplifier and/or mixer by applying full power supply voltage to the load with the bias applied to the base circuit through an operational amplifier and/or buffer circuit. For the mixer, a lower noise figure may also be realized by moving the gain control impedance from the emitter to the collector circuit. The circuits may be discrete components or part of an integrated circuit. Methods are disclosed for reducing the power supply voltage without affecting the dynamic range of an amplifier, for temperature and process parameter compensation, and for controlling the gain of a mixer without affecting input or output impedance.

Abstract: One embodiment of a circuit and corresponding method for generating a trigger signal upon the occurrence of either set up or hold time violations in the same waveform acquisition produces a trigger signal referenced to, but displaced in time from, the input clock signal. Transitions (13) in a data signal initiate a window pulse (14') whose duration is equal to the sum of a set up time requirement and a hold time requirement. The window pulse is used as the D input to a flip-flop (20) that is clocked by a version of a clock signal whose active edge has been delayed (28) for an interval that corresponds to the hold time requirement. The output of the flip-flop (20) is a trigger signal that only occurs when a set up or hold time violation has occurred. In another embodiment, triggers generated as the result of a set up time violation are referenced to the clock edge, while triggers that are generated as the result of a hold time violation are referenced to a transition in the data signal.

Abstract: A timer circuit provides a wide range of precise and substantially accurate time intervals. The timer circuit includes a ramp generator circuit having a first input for receiving an input signal to start a ramp signal, a second input for receiving a ramp timing control signal, and an output for providing a ramp signal. A comparator has a first input coupled to the output of the ramp generator, a second input coupled to a reference voltage source, and an output for providing an end ramp signal. A counter circuit has a first input for receiving the end ramp signal to begin counting, a second input for receiving a counter timing control signal, and an output for providing a terminal count signal. The end ramp signal and the terminal count signal are combined in an AND gate to provide a signal that is delayed by a predetermined amount from the input signal.

Abstract: A timer circuit provides a wide range of precise and substantially accurate time intervals. The timer circuit includes a ramp generator circuit having a first input for receiving an input signal to start a ramp signal, a second input for receiving a ramp timing conrol signal, and an output for providing a ramp signal. A comparator has a first input coupled to the output of the ramp generator, a second input coupled to a reference voltage source, and an output for providing an end ramp signal. A counter circuit has a first input for receiving the end ramp signal to begin counting, a second input for receiving a counter timing control signal, and an output for providing a terminal count signal. The end ramp signal and the terminal count signal are combined in an AND gate to provide a signal that is delayed by a predetermined amount from the input signal.

Abstract: A trigger circuit (20, 50, 80, 90, 100) suitable for triggering an oscilloscope on the occurrence of a limited amplitude input signal includes a first comparator (38) for comparing an input signal to a first, low threshold voltage and for generating a first logic signal, and a second comparator (40) for comparing the input signal to a second, high threshold voltage and for generating a second logic signal. The first and second logic signals are combined in a flip-flop circuit (25) to provided an output logic signal such that the output signal changes logic state subsequent to the input signal crossing and recrossing the first, low threshold voltage without crossing the second, high threshold voltage.

Abstract: A circuit for detecting positive and negative pulses of a predetermined maximum duration of an input signal includes a first monostable circuit for generating a first pulse having a duration equal to the predetermined maximum duration when a positive-going edge of a pulse occurs in the input signal. A second monostable circuit is provided for generating a second pulse also having a duration equal to the predetermined maximum duration when a negative-going edge of a pulse occurs in the input signal. An AND gate is coupled to the output of the first and second monostable circuits for generating a signal having a third pulse equal to the period of time both of the first and second pulses occur simultaneously. A flip-flop is coupled to the output of the AND gate for generating an output signal of a first logic state when the third pulse is generated.