Patents by Inventor Carsten Schaeffer

Carsten Schaeffer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230395539
    Abstract: A method of manufacturing a semiconductor device includes forming a wiring metal layer structure; forming a dielectric layer structure arranged directly on the wiring metal layer structure; and forming a bonding pad metal layer structure arranged, at least partially, directly on the dielectric layer structure, wherein a layer thickness of the dielectric layer structure ranges from 1% to 30% of a layer thickness of the wiring metal layer structure, wherein the wiring metal layer structure and the bonding pad metal structure are electrically connected through openings in the dielectric layer structure.
    Type: Application
    Filed: August 18, 2023
    Publication date: December 7, 2023
    Inventors: Evelyn Napetschnig, Jens Brandenburg, Christoffer Erbert, Joachim Hirschler, Oliver Humbel, Thomas Rupp, Carsten Schaeffer, Julia Zischang
  • Publication number: 20230343726
    Abstract: A high voltage semiconductor device includes a semiconductor substrate including an upper surface, a high voltage electrically conductive structure disposed on the semiconductor substrate, a first step topography at an edge of the high voltage electrically conductive structure, a varying lateral doping zone disposed within the semiconductor substrate, and a layer stack including an electrically insulating buffer layer, a SiC layer over the electrically insulating buffer layer, and a silicon nitride layer over the SiC layer or a nitrided surface region of the SiC layer, wherein the layer stack conforms to the first step topography and extends over the varying lateral doping zone.
    Type: Application
    Filed: June 28, 2023
    Publication date: October 26, 2023
    Inventors: Angelika Koprowski, Oliver Humbel, Markus Kahn, Carsten Schaeffer
  • Patent number: 11764176
    Abstract: A semiconductor device is proposed. The semiconductor device includes a wiring metal layer structure. The semiconductor device further includes a dielectric layer structure arranged directly on the wiring metal layer structure. The semiconductor device further includes a bonding pad metal layer structure arranged, at least partly, directly on the dielectric layer structure. A layer thickness of the dielectric layer structure ranges from 1% to 30% of a layer thickness of the wiring metal layer structure. The wiring metal layer structure and the bonding pad metal structure are electrically connected through openings in the dielectric layer structure.
    Type: Grant
    Filed: August 12, 2021
    Date of Patent: September 19, 2023
    Assignee: Infineon Technologies AG
    Inventors: Evelyn Napetschnig, Jens Brandenburg, Christoffer Erbert, Joachim Hirschler, Oliver Humbel, Thomas Rupp, Carsten Schaeffer, Julia Zischang
  • Publication number: 20230274996
    Abstract: A chip arrangement is provided. The chip arrangement may include a chip including a first main surface, wherein the first main surface includes an active area, a chip termination portion, and at least one contact pad. A first dielectric layer at least partially covers the chip termination portion and the active area, and at least partially exposes the at least one contact pad, and a second dielectric layer formed by atomic layer deposition over the first dielectric layer and over the at least one contact pad.
    Type: Application
    Filed: February 3, 2023
    Publication date: August 31, 2023
    Applicant: Infineon Technologies AG
    Inventors: Stefan SCHWAB, Edward FÜRGUT, Edmund RIEDL, Harry SAX, Stefan KRIVEC, Manfred PFAFFENLEHNER, Carsten SCHAEFFER
  • Publication number: 20230154978
    Abstract: A semiconductor device and a method of forming a semiconductor device are provided. In an embodiment, the semiconductor device comprises a device region, an edge termination region surrounding the device region, a first metal feature in the edge termination region, a first conformal ion diffusion barrier layer over the first metal feature, and a first conformal chemical protection layer over the first conformal ion diffusion barrier layer.
    Type: Application
    Filed: November 15, 2021
    Publication date: May 18, 2023
    Inventors: Carsten SCHAEFFER, Patrick HANEKAMP, Oliver HUMBEL, Angelika KOPROWSKI, Wolfgang LEHNERT, Francisco Javier SANTOS RODRIGUEZ
  • Publication number: 20220199464
    Abstract: A semiconductor device and a method of manufacturing a semiconductor are provided. In an embodiment, a metallic layer may be formed over a semiconductor substrate. An anti-reflective layer may be formed over the metallic layer. A passivation layer may be formed over the anti-reflective layer. An opening may be formed in the passivation layer to expose the anti-reflective layer.
    Type: Application
    Filed: December 21, 2020
    Publication date: June 23, 2022
    Inventors: Stephan VOSS, Alexander BREYMESSER, Eva-Maria HOF, Mathias PLAPPERT, Carsten SCHAEFFER
  • Publication number: 20220059477
    Abstract: A semiconductor device is proposed. The semiconductor device includes a wiring metal layer structure. The semiconductor device further includes a dielectric layer structure arranged directly on the wiring metal layer structure. The semiconductor device further includes a bonding pad metal layer structure arranged, at least partly, directly on the dielectric layer structure. A layer thickness of the dielectric layer structure ranges from 1% to 30% of a layer thickness of the wiring metal layer structure. The wiring metal layer structure and the bonding pad metal structure are electrically connected through openings in the dielectric layer structure.
    Type: Application
    Filed: August 12, 2021
    Publication date: February 24, 2022
    Inventors: Evelyn Napetschnig, Jens Brandenburg, Christoffer Erbert, Joachim Hirschler, Oliver Humbel, Thomas Rupp, Carsten Schaeffer, Julia Zischang
  • Patent number: 11171049
    Abstract: According to various embodiments, a device may include: a semiconductor region; a metallization layer disposed over the semiconductor region; and a self-organizing barrier layer disposed between the metallization layer and the semiconductor region, wherein the self-organizing barrier layer comprises a first metal configured to be self-segregating from the metallization layer.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: November 9, 2021
    Assignee: Infineon Technologies AG
    Inventors: Werner Robl, Michael Fugger, Carsten Schaeffer, Michael Nelhiebel, Klemens Pruegl
  • Patent number: 11139375
    Abstract: According to an embodiment of a method described herein, a silicon carbide substrate is provided that includes a plurality of device regions. A front side metallization may be provided at a front side of the silicon carbide substrate. The method may further comprise providing an auxiliary structure at a backside of the silicon carbide substrate. The auxiliary structure includes a plurality of laterally separated metal portions. Each metal portion is in contact with one device region of the plurality of device regions.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: October 5, 2021
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Carsten Schaeffer, Alexander Breymesser, Bernhard Goller, Ronny Kern, Matteo Piccin, Roland Rupp, Francisco Javier Santos Rodriguez
  • Publication number: 20210151391
    Abstract: A high voltage semiconductor device includes a high voltage electrically conductive structure and a step topography at or in the vicinity of the high voltage electrically conductive structure. A layer stack covers the step topography. The layer stack includes an electrically insulating buffer layer, a SiC layer over the electrically insulating buffer layer and a silicon nitride layer over the SiC layer or a nitrided surface region of the SiC layer.
    Type: Application
    Filed: November 2, 2020
    Publication date: May 20, 2021
    Inventors: Angelika Koprowski, Oliver Humbel, Markus Kahn, Carsten Schaeffer
  • Patent number: 10777506
    Abstract: According to an embodiment of a semiconductor device, the semiconductor devices includes a metal structure electrically connected to a silicon carbide semiconductor body and a metal adhesion and barrier structure between the metal structure and the silicon carbide semiconductor body. The metal adhesion and barrier structure includes a layer comprising titanium and tungsten.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: September 15, 2020
    Assignee: Infineon Technologies AG
    Inventors: Frank Hille, Ravi Keshav Joshi, Michael Fugger, Oliver Humbel, Thomas Laska, Matthias Müller, Roman Roth, Carsten Schaeffer, Hans-Joachim Schulze, Holger Schulze, Juergen Steinbrenner, Frank Umbach
  • Publication number: 20200013859
    Abstract: According to an embodiment of a method described herein, a silicon carbide substrate is provided that includes a plurality of device regions. A front side metallization may be provided at a front side of the silicon carbide substrate. The method may further comprise providing an auxiliary structure at a backside of the silicon carbide substrate. The auxiliary structure includes a plurality of laterally separated metal portions. Each metal portion is in contact with one device region of the plurality of device regions.
    Type: Application
    Filed: July 3, 2019
    Publication date: January 9, 2020
    Inventors: Carsten SCHAEFFER, Alexander Breymesser, Bernhand Goller, Ronny Kern, Matteo Piccin, Roland Rupp, Francisco Javier Santos Rodriguez
  • Publication number: 20200013722
    Abstract: According to an embodiment of a semiconductor device, the semiconductor devices includes a metal structure electrically connected to a silicon carbide semiconductor body and a metal adhesion and barrier structure between the metal structure and the silicon carbide semiconductor body. The metal adhesion and barrier structure includes a layer comprising titanium and tungsten.
    Type: Application
    Filed: September 20, 2019
    Publication date: January 9, 2020
    Inventors: Frank Hille, Ravi Keshav Joshi, Michael Fugger, Oliver Humbel, Thomas Laska, Matthias Müller, Roman Roth, Carsten Schaeffer, Hans-Joachim Schulze, Holger Schulze, Juergen Steinbrenner, Frank Umbach
  • Patent number: 10475743
    Abstract: According to an embodiment of a semiconductor device, the semiconductor devices includes a metal structure electrically connected to a semiconductor body and a metal adhesion and barrier structure between the metal structure and the semiconductor body. The metal adhesion and barrier structure includes a first layer having titanium and tungsten, and a second layer having titanium, tungsten, and nitrogen on the first layer having titanium and tungsten.
    Type: Grant
    Filed: March 14, 2017
    Date of Patent: November 12, 2019
    Assignee: Infineon Technologies AG
    Inventors: Frank Hille, Ravi Keshav Joshi, Michael Fugger, Oliver Humbel, Thomas Laska, Matthias Mueller, Roman Roth, Carsten Schaeffer, Hans-Joachim Schulze, Holger Schulze, Juergen Steinbrenner, Frank Umbach
  • Patent number: 10410911
    Abstract: A method of fabricating a semiconductor device includes forming a buried insulation region within a substrate by processing the substrate using etching and deposition processes. A semiconductor layer is formed over the buried insulation region at a first side of the substrate. Device regions are formed in the semiconductor layer. The substrate is thinned from a second side of the substrate to expose the buried insulation region. The buried insulation region is selectively removed to expose a bottom surface of the substrate. A conductive region is formed under the bottom surface of the substrate.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: September 10, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Carsten Schaeffer, Andreas Moser, Matthias Kuenle, Matteo Dainese, Roland Rupp, Hans-Joachim Schulze
  • Publication number: 20190267283
    Abstract: According to various embodiments, a device may include: a semiconductor region; a metallization layer disposed over the semiconductor region; and a self-organizing barrier layer disposed between the metallization layer and the semiconductor region, wherein the self-organizing barrier layer comprises a first metal configured to be self-segregating from the metallization layer.
    Type: Application
    Filed: May 7, 2019
    Publication date: August 29, 2019
    Inventors: Werner Robl, Michael Fugger, Carsten Schaeffer, Michael Nelhiebel, Klemens Pruegl
  • Patent number: 10332793
    Abstract: According to various embodiments, a device may include: a semiconductor region; a metallization layer disposed over the semiconductor region; and a self-organizing barrier layer disposed between the metallization layer and the semiconductor region, wherein the self-organizing barrier layer comprises a first metal configured to be self-segregating from the metallization layer.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: June 25, 2019
    Assignee: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Werner Robl, Michael Fugger, Carsten Schaeffer, Michael Nelhiebel, Klemens Pruegl
  • Patent number: 10002930
    Abstract: Disclosed is a method. The method includes forming a metal layer on a first surface of a semiconductor body; irradiating the metal layer with particles to move metal atoms from the metal layer into the semiconductor body and form a metal atom containing region in the semiconductor body; and annealing the semiconductor body. The annealing includes heating at least the metal atom containing region to a temperature of less than 500° C.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: June 19, 2018
    Assignee: Infineon Technologies AG
    Inventors: Roland Rupp, Jens Peter Konrath, Francisco Javier Santos Rodriguez, Carsten Schaeffer, Hans-Joachim Schulze, Werner Schustereder, Guenther Wellenzohn
  • Publication number: 20180166324
    Abstract: A method of fabricating a semiconductor device includes forming a buried insulation region within a substrate by processing the substrate using etching and deposition processes. A semiconductor layer is formed over the buried insulation region at a first side of the substrate. Device regions are formed in the semiconductor layer. The substrate is thinned from a second side of the substrate to expose the buried insulation region. The buried insulation region is selectively removed to expose a bottom surface of the substrate. A conductive region is formed under the bottom surface of the substrate.
    Type: Application
    Filed: December 6, 2017
    Publication date: June 14, 2018
    Inventors: Carsten Schaeffer, Andreas Moser, Matthias Kuenle, Matteo Dainese, Roland Rupp, Hans-Joachim Schulze
  • Patent number: 9859272
    Abstract: A semiconductor device comprising a source region being electrically connected to a first load terminal (E) of the semiconductor device and a drift region comprising a first semiconductor material (M1) having a first band gap, the drift region having dopants of a first conductivity type and being configured to carry at least a part of a load current between the first load terminal (E) and a second load terminal (C) of the semiconductor device, is presented. The semiconductor device further comprises a semiconductor body region having dopants of a second conductivity type complementary to the first conductivity type and being electrically connected to the first load terminal (E), a transition between the semiconductor body region and the drift region forming a pn-junction, wherein the pn-junction is configured to block a voltage applied between the first load terminal (E) and the second load terminal (C).
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: January 2, 2018
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Holger Huesken, Franz-Josef Niedernostheide, Frank Dieter Pfirsch, Roman Roth, Christian Philipp Sandow, Carsten Schaeffer, Stephan Voss