Patents by Inventor Carsten Schaeffer

Carsten Schaeffer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10332793
    Abstract: According to various embodiments, a device may include: a semiconductor region; a metallization layer disposed over the semiconductor region; and a self-organizing barrier layer disposed between the metallization layer and the semiconductor region, wherein the self-organizing barrier layer comprises a first metal configured to be self-segregating from the metallization layer.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: June 25, 2019
    Assignee: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Werner Robl, Michael Fugger, Carsten Schaeffer, Michael Nelhiebel, Klemens Pruegl
  • Patent number: 10002930
    Abstract: Disclosed is a method. The method includes forming a metal layer on a first surface of a semiconductor body; irradiating the metal layer with particles to move metal atoms from the metal layer into the semiconductor body and form a metal atom containing region in the semiconductor body; and annealing the semiconductor body. The annealing includes heating at least the metal atom containing region to a temperature of less than 500° C.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: June 19, 2018
    Assignee: Infineon Technologies AG
    Inventors: Roland Rupp, Jens Peter Konrath, Francisco Javier Santos Rodriguez, Carsten Schaeffer, Hans-Joachim Schulze, Werner Schustereder, Guenther Wellenzohn
  • Publication number: 20180166324
    Abstract: A method of fabricating a semiconductor device includes forming a buried insulation region within a substrate by processing the substrate using etching and deposition processes. A semiconductor layer is formed over the buried insulation region at a first side of the substrate. Device regions are formed in the semiconductor layer. The substrate is thinned from a second side of the substrate to expose the buried insulation region. The buried insulation region is selectively removed to expose a bottom surface of the substrate. A conductive region is formed under the bottom surface of the substrate.
    Type: Application
    Filed: December 6, 2017
    Publication date: June 14, 2018
    Inventors: Carsten Schaeffer, Andreas Moser, Matthias Kuenle, Matteo Dainese, Roland Rupp, Hans-Joachim Schulze
  • Patent number: 9859395
    Abstract: A semiconductor device includes a semiconductor body with a first surface, a contact electrode arranged on the first surface, and a passivation layer on the first surface adjacent the contact electrode. The passivation layer includes a layer stack with an amorphous semi-insulating layer on the first surface, a first nitride layer on the amorphous semi-insulating layer, and a second nitride layer on the first nitride layer.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: January 2, 2018
    Assignee: Infineon Technologies AG
    Inventors: Gerhard Schmidt, Josef-Georg Bauer, Carsten Schaeffer, Oliver Humbel, Angelika Koprowski, Sirinpa Monayakul
  • Patent number: 9859272
    Abstract: A semiconductor device comprising a source region being electrically connected to a first load terminal (E) of the semiconductor device and a drift region comprising a first semiconductor material (M1) having a first band gap, the drift region having dopants of a first conductivity type and being configured to carry at least a part of a load current between the first load terminal (E) and a second load terminal (C) of the semiconductor device, is presented. The semiconductor device further comprises a semiconductor body region having dopants of a second conductivity type complementary to the first conductivity type and being electrically connected to the first load terminal (E), a transition between the semiconductor body region and the drift region forming a pn-junction, wherein the pn-junction is configured to block a voltage applied between the first load terminal (E) and the second load terminal (C).
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: January 2, 2018
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Holger Huesken, Franz-Josef Niedernostheide, Frank Dieter Pfirsch, Roman Roth, Christian Philipp Sandow, Carsten Schaeffer, Stephan Voss
  • Publication number: 20170271268
    Abstract: According to an embodiment of a semiconductor device, the semiconductor devices includes a metal structure electrically connected to a semiconductor body and a metal adhesion and barrier structure between the metal structure and the semiconductor body. The metal adhesion and barrier structure includes a first layer having titanium and tungsten, and a second layer having titanium, tungsten, and nitrogen on the first layer having titanium and tungsten.
    Type: Application
    Filed: March 14, 2017
    Publication date: September 21, 2017
    Inventors: Frank Hille, Ravi Keshav Joshi, Michael Fugger, Oliver Humbel, Thomas Laska, Matthias Mueller, Roman Roth, Carsten Schaeffer, Hans-Joachim Schulze, Holger Schulze, Juergen Steinbrenner, Frank Umbach
  • Patent number: 9711621
    Abstract: A trench transistor having a semiconductor body includes a source region, a body region, a drain region electrically connected to a drain contact, and a gate trench including a gate electrode which is isolated from the semiconductor body. The gate electrode is configured to control current flow between the source region and the drain region along at least a first side wall of the gate trench. The trench transistor further includes a doped semiconductor region having dopants introduced into the semiconductor body through an unmasked part of the walls of a trench.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: July 18, 2017
    Assignee: Infineon Technologies AG
    Inventors: Franz Hirler, Uwe Wahl, Thorsten Meyer, Michael Rüb, Armin Willmeroth, Markus Schmitt, Carolin Tolksdorf, Carsten Schaeffer
  • Publication number: 20170162390
    Abstract: Disclosed is a method. The method includes forming a metal layer on a first surface of a semiconductor body; irradiating the metal layer with particles to move metal atoms from the metal layer into the semiconductor body and form a metal atom containing region in the semiconductor body; and annealing the semiconductor body. The annealing includes heating at least the metal atom containing region to a temperature of less than 500° C.
    Type: Application
    Filed: November 30, 2016
    Publication date: June 8, 2017
    Inventors: Roland Rupp, Jens Peter Konrath, Francisco Javier Santos Rodriguez, Carsten Schaeffer, Hans-Joachim Schulze, Werner Schustereder, Guenther Wellenzohn
  • Publication number: 20170154813
    Abstract: According to various embodiments, a device may include: a semiconductor region; a metallization layer disposed over the semiconductor region; and a self-organizing barrier layer disposed between the metallization layer and the semiconductor region, wherein the self-organizing barrier layer comprises a first metal configured to be self-segregating from the metallization layer.
    Type: Application
    Filed: November 30, 2015
    Publication date: June 1, 2017
    Inventors: Werner Robl, Michael Fugger, Carsten Schaeffer, Michael Nelhiebel, Klemens Pruegl
  • Patent number: 9571087
    Abstract: According to an embodiment of a method, a semiconductor device is operated in a reverse biased unipolar mode before operating the semiconductor device in an off-state in a forward biased mode. The semiconductor device includes at least one floating parasitic region disposed outside a cell region of the device.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: February 14, 2017
    Assignee: Infineon Technologies AG
    Inventors: Frank Pfirsch, Dorothea Werber, Anton Mauder, Carsten Schaeffer
  • Publication number: 20170025408
    Abstract: A semiconductor device comprising a source region being electrically connected to a first load terminal (E) of the semiconductor device and a drift region comprising a first semiconductor material (M1) having a first band gap, the drift region having dopants of a first conductivity type and being configured to carry at least a part of a load current between the first load terminal (E) and a second load terminal (C) of the semiconductor device, is presented. The semiconductor device further comprises a semiconductor body region having dopants of a second conductivity type complementary to the first conductivity type and being electrically connected to the first load terminal (E), a transition between the semiconductor body region and the drift region forming a pn-junction, wherein the pn-junction is configured to block a voltage applied between the first load terminal (E) and the second load terminal (C).
    Type: Application
    Filed: July 14, 2016
    Publication date: January 26, 2017
    Inventors: Hans-Joachim Schulze, Holger Huesken, Franz-Josef Niedernostheide, Frank Dieter Pfirsch, Roman Roth, Christian Philipp Sandow, Carsten Schaeffer, Stephan Voss
  • Publication number: 20160226477
    Abstract: According to an embodiment of a method, a semiconductor device is operated in a reverse biased unipolar mode before operating the semiconductor device in an off-state in a forward biased mode The semiconductor device includes at least one floating parasitic region disposed outside a cell region of the device.
    Type: Application
    Filed: December 9, 2015
    Publication date: August 4, 2016
    Inventors: Frank Pfirsch, Dorothea Werber, Anton Mauder, Carsten Schaeffer
  • Patent number: 9362349
    Abstract: A semiconductor device includes a cell region having at least one device cell, wherein the at least one device cell includes a first device region of a first conductivity type. The semiconductor device further includes a drift region of a second conductivity type adjoining the first device region of the at least one device cell, a doped region of the first conductivity type adjoining the drift region, and charge carrier lifetime reduction means configured to reduce a charge carrier lifetime in the doped region of the first conductivity type.
    Type: Grant
    Filed: June 21, 2013
    Date of Patent: June 7, 2016
    Assignee: Infineon Technologies AG
    Inventors: Dorothea Werber, Frank Pfirsch, Hans-Joachim Schulze, Carsten Schaeffer, Volodymyr Komarnitskyy, Anton Mauder, Holger Schulze, Gerhard Miller
  • Patent number: 9355958
    Abstract: A semiconductor device includes a semiconductor substrate having a first side, a second side opposite the first side, an active area, an outer rim, and an edge termination area arranged between the outer rim and the active area. A metallization structure is arranged on the first side of the semiconductor substrate and comprising at least a first metal layer comprised of a first metallic material and a second metal layer comprised of a second metallic material, wherein the first metallic material is electrochemically more stable than the second metallic material. The first metal layer extends laterally further towards the outer rim than the second metal layer.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: May 31, 2016
    Assignee: Infineon Technologies AG
    Inventors: Carsten Schäffer, Oliver Humbel, Mathias Plappert, Angelika Koprowski
  • Patent number: 9337185
    Abstract: A semiconductor device includes a first doping region extending from a main surface of a semiconductor substrate into the semiconductor substrate. Further, the semiconductor device includes a second doping region arranged adjacent to the first doping region. The first doping region includes at least one low doping dose portion extending from the main surface of the semiconductor substrate to the second doping region. A doping dose within the low doping dose portion of the first doping region is less than 3 times a breakdown charge. Additionally, the semiconductor device includes a first electrode structure in contact with the first doping region at the main surface of the semiconductor substrate. The work function of the first electrode structure at the main surface of the semiconductor substrate is larger than 4.9 eV or lower than 4.4 eV.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: May 10, 2016
    Assignee: Infineon Technologies AG
    Inventors: Frank Pfirsch, Dorothea Werber, Carsten Schaeffer
  • Patent number: 9231581
    Abstract: According to an embodiment of a method, a semiconductor device is operated in a reverse biased unipolar mode before operating the semiconductor device in an off-state in a forward biased mode. The semiconductor device includes at least one floating parasitic region disposed outside a cell region of the device.
    Type: Grant
    Filed: November 24, 2014
    Date of Patent: January 5, 2016
    Assignee: Infineon Technologies AG
    Inventors: Frank Pfirsch, Dorothea Werber, Anton Mauder, Carsten Schaeffer
  • Patent number: 9214521
    Abstract: A semiconductor device includes a first emitter region of a first conductivity type, a second emitter region of a second conductivity type complementary to the first type, a drift region of the second conductivity type, and a first electrode. The first and second emitter regions are arranged between the drift region and first electrode and each connected to the first electrode. A device cell of a cell region includes a body region of the first conductivity type adjoining the drift region, a source region of the second conductivity type adjoining the body region, and a gate electrode adjacent the body region and dielectrically insulated from the body region by a gate dielectric. A second electrode is electrically connected to the source and body regions. A parasitic region of the first conductivity type is disposed outside the cell region and includes at least one section with charge carrier lifetime reduction means.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: December 15, 2015
    Assignee: Infineon Technologies AG
    Inventors: Dorothea Werber, Frank Pfirsch, Hans-Joachim Schulze, Carsten Schaeffer, Volodymyr Komarnitskyy, Anton Mauder
  • Publication number: 20150262814
    Abstract: A power semiconductor device in accordance with various embodiments may include: a semiconductor body; and a passivation layer disposed over at least a portion of the semiconductor body, wherein the passivation layer includes an organic dielectric material having a water uptake of less than or equal to 0.5 wt % in saturation.
    Type: Application
    Filed: March 13, 2014
    Publication date: September 17, 2015
    Applicant: Infineon Technologies AG
    Inventors: Mathias Plappert, Eric Graetz, Andreas Behrendt, Oliver Humbel, Carsten Schaeffer, Angelika Koprowski
  • Publication number: 20150179637
    Abstract: A semiconductor device includes a first doping region extending from a main surface of a semiconductor substrate into the semiconductor substrate. Further, the semiconductor device includes a second doping region arranged adjacent to the first doping region. The first doping region includes at least one low doping dose portion extending from the main surface of the semiconductor substrate to the second doping region. A doping dose within the low doping dose portion of the first doping region is less than 3 times a breakdown charge. Additionally, the semiconductor device includes a first electrode structure in contact with the first doping region at the main surface of the semiconductor substrate. The work function of the first electrode structure at the main surface of the semiconductor substrate is larger than 4.9 eV or lower than 4.4 eV.
    Type: Application
    Filed: December 5, 2014
    Publication date: June 25, 2015
    Inventors: Frank Pfirsch, Dorothea Werber, Carsten Schaeffer
  • Publication number: 20150115449
    Abstract: A semiconductor device includes a semiconductor substrate having a first side, a second side opposite the first side, an active area, an outer rim, and an edge termination area arranged between the outer rim and the active area. A metallization structure is arranged on the first side of the semiconductor substrate and comprising at least a first metal layer comprised of a first metallic material and a second metal layer comprised of a second metallic material, wherein the first metallic material is electrochemically more stable than the second metallic material. The first metal layer extends laterally further towards the outer rim than the second metal layer.
    Type: Application
    Filed: October 31, 2013
    Publication date: April 30, 2015
    Inventors: Carsten Schäffer, Oliver Humbel, Mathias Plappert, Angelika Koprowski