Patents by Inventor Casey R. Kurth
Casey R. Kurth has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7440255Abstract: A capacitor construction includes a first electrode and a layer between the first electrode and a surface supporting the capacitor construction. The capacitor construction can exhibit a lower RC time constant compared to an otherwise identical capacitor construction lacking the layer. Alternatively, or additionally, the first electrode may contain Si and the layer may limit the Si from contributing to formation of metal silicide material between the first electrode and the supporting surface. The layer may be a nitride layer and may be conductive or insulative. When conductive, the layer may exhibit a first conductivity greater than a second conductivity of the first electrode. The capacitor construction may be used in memory devices.Type: GrantFiled: July 21, 2003Date of Patent: October 21, 2008Assignee: Micron Technology, Inc.Inventors: Brent A. McClure, Casey R. Kurth, Shenlin Chen, Debra K. Gould, Lyle D. Breiner, Er-Xuan Ping, Fred D. Fishburn, Hongmei Wang
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Patent number: 6903991Abstract: Circuitry for programming antifuse elements is provided which permits all antifuse elements in a bank to be programmed simultaneously, thereby enhancing the speed at which antifuse elements may be programmed. In one embodiment, a feedback circuit is associated with each antifuse element to stop the flow of current through the antifuse element once it is programmed. In another embodiment, circuitry is provided for generating a separate programming pulse for each antifuse element, which is selected for programming.Type: GrantFiled: June 24, 2002Date of Patent: June 7, 2005Assignee: Micron Technology, Inc.Inventors: Patrick J. Mullarkey, Casey R. Kurth, Jason Graalum, Daryl L. Habersetzer
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Patent number: 6834022Abstract: A memory device includes an address selection circuit to store addresses of selected rows of memory cells. During a refresh mode, only the memory cells of the selected rows are refreshed. The addresses of the selected rows can be stored automatically by the memory device during a memory operation mode or manually by a user during a programming mode.Type: GrantFiled: November 18, 2003Date of Patent: December 21, 2004Assignee: Micron Technology, Inc.Inventors: Scott J. Derner, Casey R. Kurth, Daryl L. Habersetzer
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Patent number: 6826071Abstract: A method of verifying whether unprogrammed antifuses are leaky in a semiconductor memory. The method involves the steps of: connecting the antifuse in series with a node; providing current to the node, the current being sufficient to charge the node from a first to a second voltage; detecting whether the voltage at the node charges to the second voltage, or remains at the first voltage to indicate that the antifuse is leaky; outputting signals indicating the result of the detection; and detecting the voltage at the node remains at the first voltage indicates that the antifuse is leaky. In another embodiment, a method of verifying whether antifuses have been programmed properly in a semiconductor memory.Type: GrantFiled: March 15, 2002Date of Patent: November 30, 2004Assignee: Micron Technology, Inc.Inventors: Patrick J. Mullarkey, Casey R. Kurth, Jason Graalum, Daryl L. Habersetzer
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Publication number: 20040223397Abstract: A method of verifying whether unprogrammed antifuses are leaky in a semiconductor memory. The method involves the steps of: connecting the antifuse in series with a node; providing current to the node, the current being sufficient to charge the node from a first to a second voltage; detecting whether the voltage at the node charges to the second voltage, or remains at the first voltage to indicate that the antifuse is leaky; outputting signals indicating the result of the detection; and detecting the voltage at the node remains at the first voltage indicates that the antifuse is leaky. In another embodiment, a method of verifying whether antifuses have been programmed properly in a semiconductor memory.Type: ApplicationFiled: March 15, 2002Publication date: November 11, 2004Applicant: MICRON TECHNOLOGY, INC.Inventors: Patick J. Mullarkey, Casey R. Kurth, Jason Graalum, Daryl L. Habersetzer
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Publication number: 20040100847Abstract: A memory device includes an address selection circuit to store addresses of selected rows of memory cells. During a refresh mode, only the memory cells of the selected rows are refreshed. The addresses of the selected rows can be stored by a user or automatically.Type: ApplicationFiled: November 18, 2003Publication date: May 27, 2004Applicant: Micron Technology, Inc.Inventors: Scott J. Derner, Casey R. Kurth, Daryl L. Habersetzer
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Patent number: 6724238Abstract: An apparatus and method for improving the gate oxide reliability of an antifuse circuit is provided by coupling the gate input of a protection device of the antiftise circuit to a voltage converter circuit. In a program mode, a first voltage is applied through the voltage converter circuit to the gate input of the protection device to limit the voltage passed to internal transistor devices, thus increasing their gate oxide reliability. In a normal operation mode, however, a second, lower voltage is applied through the voltage converter to the gate input of the protection device to remove the large voltage stress placed across the gate oxide of the protection device itself. The voltage converter may attenuate the first voltage to create the second voltage or it may switch its output between the first and second voltage levels.Type: GrantFiled: May 29, 2003Date of Patent: April 20, 2004Assignee: Micron Technology, Inc.Inventors: Scott J. Derner, Casey R. Kurth
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Publication number: 20030234679Abstract: An apparatus and method for improving the gate oxide reliability of an antifuse circuit is provided by coupling the gate input of a protection device of the antifuse circuit to a voltage converter circuit. In a program mode, a first voltage is applied through the voltage converter circuit to the gate input of the protection device to limit the voltage passed to internal transistor devices, thus increasing their gate oxide reliability. In a normal operation mode, however, a second, lower voltage is applied through the voltage converter to the gate input of the protection device to remove the large voltage stress placed across the gate oxide of the protection device itself. The voltage converter may attenuate the first voltage to create the second voltage or it may switch its output between the first and second voltage levels.Type: ApplicationFiled: May 29, 2003Publication date: December 25, 2003Inventors: Scott J. Derner, Casey R. Kurth
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Patent number: 6661693Abstract: Circuitry for programming antifuse elements is provided which permits all antifuse elements in a bank to be programmed simultaneously, thereby enhancing the speed at which antifuse elements may be programmed. In one embodiment, a feedback circuit is associated with each antifuse element to stop the flow of current through the antifuse element once it is programmed. In another embodiment, circuitry is provided for generating a separate programming pulse for each antifuse element, which is selected for programming.Type: GrantFiled: June 24, 2002Date of Patent: December 9, 2003Assignee: Micron TechnologyInventors: Patrick J. Mullarkey, Casey R. Kurth, Jason Graalum, Daryl L. Habersetzer
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Patent number: 6650587Abstract: A memory device includes an address selection circuit to store addresses of selected rows of memory cells. During a refresh mode, only the memory cells of the selected rows are refreshed. The addresses of the selected rows can be stored by a user or automatically.Type: GrantFiled: November 19, 2001Date of Patent: November 18, 2003Assignee: Micron Technology, Inc.Inventors: Scott J. Derner, Casey R. Kurth, Daryl L. Habersetzer
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Patent number: 6646459Abstract: A test-mode latching circuit residing on an integrated circuit with test circuitry and operational circuitry has an enable state and a disable state. In the enable state, a test key is able to be latched so as to trigger a test mode. In the disable state, test key inputs are not latched, and thus, test modes are not entered. Initially, the circuit is readily enabled so that the IC can be tested upon fabrication. The circuit is locked in a disable state before external sale. A re-enable circuit is present to preclude inadvertent switching of the latching circuit back into the enable state during customer operation. Safeguards are implemented to avoid inadvertently re-enabling the latching circuit. To re-enable the latching circuit, an out-of-spec voltage is applied to an anti-fuse capacitor or programmable logic circuit while an out-of-spec voltage of the same or another signal is detected at a field device. In one embodiment, the state switches to the enable state in response to the out-of-spec voltage.Type: GrantFiled: March 19, 2001Date of Patent: November 11, 2003Assignee: Micron Technology, Inc.Inventors: Daryl L. Habersetzer, Casey R. Kurth, Patrick J. Mullarkey, Jason E. Graalum
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Publication number: 20030185080Abstract: A method of verifying whether unprogrammed antifuses are leaky in a semiconductor memory. The method involves the steps of: connecting the antifuse in series with a node; providing current to the node, the current being sufficient to charge the node from a first to a second voltage; detecting whether the voltage at the node charges to the second voltage, or remains at the first voltage to indicate that the antifuse is leaky; outputting signals indicating the result of the detection; and detecting the voltage at the node remains at the first voltage indicates that the antifuse is leaky. In another embodiment, a method of verifying whether antifuses have been programmed properly in a semiconductor memory.Type: ApplicationFiled: March 15, 2002Publication date: October 2, 2003Applicant: MICRON TECHNOLOGY, INC.Inventors: Patick J. Mullarkey, Casey R. Kurth, Jason Graalum, Daryl L. Habersetzer
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Patent number: 6611165Abstract: An apparatus and method for improving the gate oxide reliability of an antifuse circuit is provided by coupling the gate input of a protection device of the antifuse circuit to a voltage converter circuit. In a program mode, a first voltage is applied through the voltage converter circuit to the gate input of the protection device to limit the voltage passed to internal transistor devices, thus increasing their gate oxide reliability. In a normal operation mode, however, a second, lower voltage is applied through the voltage converter to the gate input of the protection device to remove the large voltage stress placed across the gate oxide of the protection device itself. The voltage converter may attenuate the first voltage to create the second voltage or it may switch its output between the first and second voltage levels.Type: GrantFiled: June 25, 2002Date of Patent: August 26, 2003Assignee: Micron Technology, Inc.Inventors: Scott J. Derner, Casey R. Kurth
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Patent number: 6590407Abstract: A test-mode latching circuit residing on an integrated circuit with test circuitry and operational circuitry has an enable state and a disable state. In the enable state, a test key is able to be latched so as to trigger a test mode. In the disable state, test key inputs are not latched, and thus, test modes are not entered. Initially, the circuit is readily enabled so that the IC can be tested upon fabrication. The circuit is locked in a disable state before external sale. A re-enable circuit is present to preclude inadvertent switching of the latching circuit back into the enable state during customer operation. Safeguards are implemented to avoid inadvertently re-enabling the latching circuit. To re-enable the latching circuit, an out-of-spec voltage is applied to an anti-fuse capacitor or programmable logic circuit while an out-of-spec voltage of the same or another signal is detected at a field device. In one embodiment, the state switches to the enable state in response to the out-of-spec voltage.Type: GrantFiled: August 16, 2002Date of Patent: July 8, 2003Assignee: Micron Technology, Inc.Inventors: Daryl L. Habersetzer, Casey R. Kurth, Patrick J. Mullarkey, Jason E. Graalum
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Patent number: 6570400Abstract: A test-mode latching circuit residing on an integrated circuit with test circuitry and operational circuitry has an enable state and a disable state. In the enable state, a test key is able to be latched so as to trigger a test mode. In the disable state, test key inputs are not latched and, thus, test modes are not entered. Initially, the circuit is readily enabled so that the IC can be tested upon fabrication. The circuit is locked in a disable state before external sale. A re-enable circuit is present to preclude inadvertent switching of the latching circuit back into the enable state during customer operation. Safeguards are implemented to avoid inadvertently re-enabling the latching circuit. To re-enable the latching circuit, an out-of-spec voltage is applied to an anti-fuse capacitor or programmable logic circuit while an out-of-spec voltage of the same or another signal is detected at a field device. In one embodiment, the state switches to the enable state in response to the out-of-spec voltage.Type: GrantFiled: March 29, 2002Date of Patent: May 27, 2003Assignee: Micron Technology, Inc.Inventors: Daryl L. Habersetzer, Casey R. Kurth, Patrick J. Mullarkey, Jason E. Graalum
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Publication number: 20030095459Abstract: A memory device includes an address selection circuit to store addresses of selected rows of memory cells. During a refresh mode, only the memory cells of the selected rows are refreshed. The addresses of the selected rows can be stored by a user or automatically.Type: ApplicationFiled: November 19, 2001Publication date: May 22, 2003Applicant: Micron Technology, Inc.Inventors: Scott J. Derner, Casey R. Kurth, Daryl L. Habersetzer
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Publication number: 20030020508Abstract: A test-mode latching circuit residing on an integrated circuit with test circuitry and operational circuitry has an enable state and a disable state. In the enable state, a test key is able to be latched so as to trigger a test mode. In the disable state, test key inputs are not latched, and thus, test modes are not entered. Initially, the circuit is readily enabled so that the IC can be tested upon fabrication. The circuit is locked in a disable state before external sale. A re-enable circuit is present to preclude inadvertent switching of the latching circuit back into the enable state during customer operation. Safeguards are implemented to avoid inadvertently re-enabling the latching circuit. To re-enable the latching circuit, an out-of-spec voltage is applied to an anti-fuse capacitor or programmable logic circuit while an out-of-spec voltage of the same or another signal is detected at a field device. In one embodiment, the state switches to the enable state in response to the out-of-spec voltage.Type: ApplicationFiled: August 16, 2002Publication date: January 30, 2003Inventors: Daryl L. Habersetzer, Casey R. Kurth, Patrick J. Mullarkey, Jason E. Graalum
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Publication number: 20020167831Abstract: Circuitry for programming antifuse elements is provided which permits all antifuse elements in a bank to be programmed simultaneously, thereby enhancing the speed at which antifuse elements may be programmed. In one embodiment, a feedback circuit is associated with each antifuse element to stop the flow of current through the antifuse element once it is programmed. In another embodiment, circuitry is provided for generating a separate programming pulse for each antifuse element, which is selected for programming.Type: ApplicationFiled: June 24, 2002Publication date: November 14, 2002Applicant: MICRON TECHNOLOGY, INC.Inventors: Patrick J. Mullarkey, Casey R. Kurth, Jason Graalum, Daryl L. Habersetzer
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Publication number: 20020163827Abstract: Circuitry for programming antifuse elements is provided which permits all antifuse elements in a bank to be programmed simultaneously, thereby enhancing the speed at which antifuse elements may be programmed. In one embodiment, a feedback circuit is associated with each antifuse element to stop the flow of current through the antifuse element once it is programmed. In another embodiment, circuitry is provided for generating a separate programming pulse for each antifuse element, which is selected for programming.Type: ApplicationFiled: June 24, 2002Publication date: November 7, 2002Applicant: MICRON TECHNOLOGY, INC.Inventors: Patrick J. Mullarkey, Casey R. Kurth, Jason Graalum, Daryl L. Habersetzer
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Publication number: 20020140449Abstract: A test-mode latching circuit residing on an integrated circuit with test circuitry and operational circuitry has an enable state and a disable state. In the enable state, a test key is able to be latched so as to trigger a test mode. In the disable state, test key inputs are not latched and, thus, test modes are not entered. Initially, the circuit is readily enabled so that the IC can be tested upon fabrication. The circuit is locked in a disable state before external sale. A re-enable circuit is present to preclude inadvertent switching of the latching circuit back into the enable state during customer operation. Safeguards are implemented to avoid inadvertently re-enabling the latching circuit. To re-enable the latching circuit, an out-of-spec voltage is applied to an anti-fuse capacitor or programmable logic circuit while an out-of-spec voltage of the same or another signal is detected at a field device. In one embodiment, the state switches to the enable state in response to the out-of-spec voltage.Type: ApplicationFiled: March 29, 2002Publication date: October 3, 2002Inventors: Daryl L. Habersetzer, Casey R. Kurth, Patrick J. Mullarkey, Jason E. Graalum