Abstract: A method of verifying whether unprogrammed antifuses are leaky in a semiconductor memory. The method involves the steps of: connecting the antifuse in series with a node; providing current to the node, the current being sufficient to charge the node from a first to a second voltage; detecting whether the voltage at the node charges to the second voltage, or remains at the first voltage to indicate that the antifuse is leaky; outputting signals indicating the result of the detection; and detecting the voltage at the node remains at the first voltage indicates that the antifuse is leaky. In another embodiment, a method of verifying whether antifuses have been programmed properly in a semiconductor memory.

Abstract: A ROM is embedded within an array of DRAM cells by changing a single mask in a DRAM fabrication process to selectively short circuit the DRAM capacitor lower electrode to its own wordline to create a read-only “1” or to the wordline of an adjacent cell to create a read only “0”.

Abstract: A memory device includes a memory array, a plurality of external lines, a command buffer, and control logic. The plurality of external lines is adapted for receiving an external command. The command buffer is adapted to store at least one command buffer entry. The control logic is coupled to the plurality of external lines and the command buffer. The control logic is adapted to access the memory array based on one of the command buffer entry and the external command. A method for providing commands to a memory device is provided. The memory device includes a command buffer, control logic and a memory array. The method includes reading a first buffered command from the command buffer. The first buffered command is provided to the control logic. The memory array is accessed based on the first buffered command.

Abstract: A method and circuit for rapidly equilibrating paired digit lines of the memory array of a dynamic random access memory device during testing of the memory device includes a plurality of pass gates which are used to connect the equilibrating voltage directly to the paired digit lines, bypassing the conventional equilibration circuitry of the memory device. The pass gates used are contained in spare rows of the memory array and are fabricated as part of the memory device. The pass gates are enabled by activating the row lines for the spare rows while the memory device is being operated in a test mode.

Abstract: A ROM is embedded within an array of DRAM cells by changing a single mask in a DRAM fabrication process to selectively short circuit the DRAM capacitor lower electrode to its own wordline to create a read-only “1” or to the wordline of an adjacent cell to create a read only “0”.

Abstract: A test-mode latching circuit residing on an integrated circuit with test circuitry and operational circuitry has an enable state and a disable state. In the enable state, a test key is able to be latched so as to trigger a test mode. In the disable state, test key inputs are not latched, and thus, test modes are not entered. Initially, the circuit is readily enabled so that the IC can be tested upon fabrication. The circuit is locked in a disable state before external sale. A re-enable circuit is present to preclude inadvertent switching of the latching circuit back into the enable state during customer operation. Safeguards are implemented to avoid inadvertently re-enabling the latching circuit. To re-enable the latching circuit, an out-of-spec voltage is applied to an anti-fuse capacitor or programmable logic circuit while an out-of-spec voltage of the same or another signal is detected at a field device. In one embodiment, the state switches to the enable state in response to the out-of-spec voltage.

Abstract: A test-mode latching circuit residing on an integrated circuit with test circuitry and operational circuitry has an enable state and a disable state. In the enable state, a test key is able to be latched so as to trigger a test mode. In the disable state, test key inputs are not latched and, thus, test modes are not entered. Initially, the circuit is readily enabled so that the IC can be tested upon fabrication. The circuit is locked in a disable state before external sale. A re-enable circuit is present to preclude inadvertent switching of the latching circuit back into the enable state during customer operation. Safeguards are implemented to avoid inadvertently re-enabling the latching circuit. To re-enable the latching circuit, an out-of-spec voltage is applied to an anti-fuse capacitor or programmable logic circuit while an out-of-spec voltage of the same or another signal is detected at a field device. In one embodiment, the state switches to the enable state in response to the out-of-spec voltage.

Abstract: A test-mode latching circuit residing on an integrated circuit with test circuitry and operational circuitry has an enable state and a disable state. In the enable state, a test key is able to be latched so as to trigger a test mode. In the disable state, test key inputs are not latched and, thus, test modes are not entered. Initially, the circuit is readily enabled so that the IC can be tested upon fabrication. The circuit is locked in a disable state before external sale. A re-enable circuit is present to preclude inadvertent switching of the latching circuit back into the enable state during customer operation. Safeguards are implemented to avoid inadvertently re-enabling the latching circuit. To re-enable the latching circuit, an out-of-spec voltage is applied to an anti-fuse capacitor or programmable logic circuit while an out-of-spec voltage of the sane or another signal is detected at a field device. In one embodiment, the state switches to the enable state in response to the out-of-spec voltage.

Abstract: A memory device includes a memory array, a plurality of external lines, a command buffer, and control logic. The plurality of external lines is adapted for receiving an external command. The command buffer is adapted to store at least one command buffer entry. The control logic is coupled to the plurality of external lines and the command buffer. The control logic is adapted to access the memory array based on one of the command buffer entry and the external command. A method for providing commands to a memory device is provided. The memory device includes a command buffer, control logic and a memory array. The method includes reading a first buffered command from the command buffer. The first buffered command is provided to the control logic. The memory array is accessed based on the first buffered command.

Abstract: A ROM is embedded within an array of DRAM cells by changing a single mask in a DRAM fabrication process to selectively short circuit the DRAM capacitor lower electrode to its own wordline to create a read-only “1” or to the wordline of an adjacent cell to create a read only “0”.

Abstract: A memory device includes a memory array, a plurality of external lines, a command buffer, and control logic. The plurality of external lines is adapted for receiving an external command. The command buffer is adapted to store at least one command buffer entry. The control logic is coupled to the plurality of external lines and the command buffer. The control logic is adapted to access the memory array based on one of the command buffer entry and the external command. A method for providing commands to a memory device is provided. The memory device includes a command buffer, control logic and a memory array. The method includes reading a first buffered command from the command buffer. The first buffered command is provided to the control logic. The memory array is accessed based on the first buffered command.

Abstract: A test-mode latching circuit residing on an integrated circuit with test circuitry and operational circuitry has an enable state and a disable state. In the enable state, a test key is able to be latched so as to trigger a test mode. In the disable state, test key inputs are not latched, and thus, test modes are not entered. Initially, the circuit is readily enabled so that the IC can be tested upon fabrication. The circuit is locked in a disable state before external sale. A re-enable circuit is present to preclude inadvertent switching of the latching circuit back into the enable state during customer operation. Safeguards are implemented to avoid inadvertently re-enabling the latching circuit. To re-enable the latching circuit, an out-of-spec voltage is applied to an anti-fuse capacitor or programmable logic circuit while an out-of-spec voltage of the same or another signal is detected at a field device. In one embodiment, the state switches to the enable state in response to the out-of-spec voltage.

Abstract: A method and circuit for rapidly equilibrating paired digit lines of the memory array of a dynamic random access memory device during testing of the memory device includes a plurality of pass gates which are used to connect the equilibrating voltage directly to the paired digit lines, bypassing the conventional equilibration circuitry of the memory device. The pass gates used are contained in spare rows of the memory array and are fabricated as part of the memory device. The pass gates are enabled by activating the row lines for the spare rows while the memory device is being operated in a test mode.

Abstract: A ROM is embedded within an array of DRAM cells by changing a single mask in a DRAM fabrication process to selectively short circuit the DRAM capacitor lower electrode to its own wordline to create a read-only "1" or to the wordline of an adjacent cell to create a read only "0".

Abstract: Circuitry for programming antifuse elements is provided which permits all antifuse elements in a bank to be programmed simultaneously, thereby enhancing the speed at which antifuse elements may be programmed. In one embodiment, a feedback circuit is associated with each antifuse element to stop the flow of current through the antifuse element once it is programmed. In another embodiment, circuitry is provided for generating a separate programming pulse for each antifuse element, which is selected for programming.

Abstract: A method of verifying whether unprogrammed antifuses are leaky in a semiconductor memory. The method involves the steps of: connecting the antifuse in series with a node; providing current to the node, the current being sufficient to charge the node from a first to a second voltage; detecting whether the voltage at the node charges to the second voltage, or remains at the first voltage to indicate that the antifuse is leaky; outputting signals indicating the result of the detection; and detecting the voltage at the node remains at the first voltage indicates that the antifuse is leaky. In another embodiment, a method of verfying whether antifuses have been programmed properly in a semiconductor memory.

Abstract: A method and circuit for rapidly equilibrating paired digit lines of the memory array of a dynamic random access memory device during testing of the memory device includes a plurality of pass gates which are used to connect the equilibrating voltage directly to the paired digit lines, bypassing the conventional equilibration circuitry of the memory device. The pass gates used are contained in spare rows of the memory array and are fabricated as part of the memory device. The pass gates are enabled by activating the row lines for the spare rows while the memory device is being operated in a test mode.

Abstract: An integrated circuit package includes an integrated circuit device that operates in more than one operational mode. The operational mode of the integrated circuit device is controlled by a mode select input. Examples of operational modes include fast page and block modes, two- and three-latency modes, and normal and test modes. A reprogrammable mode select circuit within the integrated circuit package produces a mode control signal that drives a mode select input of the integrated circuit device. The operational mode of the integrated circuit device then corresponds to the state of the mode select signal.

Abstract: Circuitry for programming antifuse elements is provided which permits all antifuse elements in a bank to be programmed simultaneously, thereby enhancing the speed at which antifuse elements may be programmed. In one embodiment, a feedback circuit is associated with each antifuse element to stop the flow of current through the antifuse element once it is programmed. In another embodiment, circuitry is provided for generating a separate programming pulse for each antifuse element, which is selected for programming.

Abstract: A test-mode latching circuit residing on an integrated circuit with test circuitry and operational circuitry has an enable state and a disable state. In the enable state, a test key is able to be latched so as to trigger a test mode. In the disable state test key inputs are not latched, and thus, test modes are not entered. Initially the circuit is readily enabled so that the IC can be tested upon fabrication. The circuit is locked in a disable state before external sale. A re-enable circuit is present to preclude inadvertent switching of the latching circuit back into the enable state during customer operation. Safeguards are implemented to avoid inadvertently re-enabling the latching circuit. To re-enable the latching circuit, an out-of-spec voltage is applied to an anti-fuse capacitor or programmable logic circuit while an out-of-spec voltage of the same or another signal is detected at a field device. In one embodiment, the state switches to the enable state in response to the out-of-spec voltage.