Patents by Inventor Catherine Vartuli
Catherine Vartuli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 6870950Abstract: The present invention provides a method for detecting defects in a material and a system for accomplishing the same. The method includes obtaining an image of at least a portion of a material's surface and converting the image into an intensity profile. The method further includes determining a defect in the material's surface from the intensity profile. In one exemplary embodiment, the image is an electron image obtained using a scanning electron microscope. The method may further be used to determine a defect density in the material's surface.Type: GrantFiled: March 15, 2001Date of Patent: March 22, 2005Assignee: Agere Systems Inc.Inventors: Erik C. Houge, Catherine Vartuli, Mike Antonell, Pam Cavanagh, Hui Ma
-
Publication number: 20040229477Abstract: A method and apparatus for depositing material from a target onto a semiconductor wafer. The wafer is positioned above a chuck that is heated by a chuck heater. Radiant heat flow from the chuck to the wafer is the primary heat source for the wafer. Thus by controlling the chuck heater temperature the wafer temperature can be maintained within a desired range to effectuate desired characteristics in the deposited material.Type: ApplicationFiled: July 8, 2003Publication date: November 18, 2004Inventors: Timothy J. Daniel, Joseph W. Buckfeller, Craig C. Clabough, Catherine Vartuli
-
Patent number: 6750447Abstract: A method and apparatus used to calibrate high-resolution electron microscopes where a single standard provides multiple samples, each having a different atomic structure, permits rapid accurate calibration of the entire range of magnifications. The different atomic structure dimensions possess known reference measurement data. The S/TEM is adjusted to focus onto the crystal lattice structure of each sample in a selected sequence. Measurements of these lattice spacings are compared to known dimensions. If S/TEM measurements do not agree with the lattice spacing dimensions, the S/TEM magnification is adjusted to reflect known dimensions. Typical standard exchange and associated processing steps are eliminated by the use of the single standard comprising of a plurality of samples.Type: GrantFiled: April 12, 2002Date of Patent: June 15, 2004Assignee: Agere Systems, Inc.Inventors: Erik Cho Houge, Catherine Vartuli, John Martin McIntosh, Fred Anthony Stevie
-
Patent number: 6713409Abstract: A manufacturing method using a modular substrate-based processing scheme for producing semiconductor devices, provides multiple modular processing units which may be arranged together to form any of various cohesive processing units or individually or sequentially processed through standard semiconductor processing equipment. The cohesive processing units are processed unitarily providing for multiple modular processing units to be processed simultaneously. The modular processing units may be formed of a thick semiconductor substrate or a semiconductor substrate mounted on a further substrate such as a ceramic material. The modular processing units may each contain ribs, grooves, posts or other features to aid in handling and placement of the individual units.Type: GrantFiled: November 25, 2002Date of Patent: March 30, 2004Assignee: Agere Systems Inc.Inventors: Michael Antonell, Erik Cho Houge, Nitin Patel, Larry E. Plew, Catherine Vartuli
-
Patent number: 6708574Abstract: A semiconductor manufacturing automation method for analyzing a patterned feature formed on a semiconductor layer is disclosed. At least one patterned feature is scanned to generate an amplitude modulated waveform signal of the line and neighboring space characteristics. Signal processing is automatically performed on this waveform by an in-line computational source to extract known patterned features based on the profile of the amplitude modulated waveform signal. The extracted waveform segments are subjected to known geometric shapes to determine if the waveform indicates a normal or abnormal patterned feature on a semiconductor layer.Type: GrantFiled: May 24, 2002Date of Patent: March 23, 2004Assignee: Agere Systems, Inc.Inventors: Erik Cho Houge, Scott Jessen, John Martin McIntosh, Catherine Vartuli, Fred Anthony Stevie
-
Patent number: 6695572Abstract: A method and apparatus for minimizing the surface contamination of semiconductor wafers (11) during the semiconductor device manufacturing process. Semiconductor wafers (11) are stored in a storage cassette (12) with their face sides (17) facing downward and their back sides (16) facing upward. Particulate contamination present on the back sides of the wafers is thereby secured to the wafers by the force of gravity, and the faces of the wafers are shielded from falling debris. An automated wafer handling device (19) is provided with a rotary joint (22) to accomplish the wafer flipping motion before inserting a wafer into a cassette and after removing the wafer from the cassette.Type: GrantFiled: September 28, 2001Date of Patent: February 24, 2004Assignee: Agere Systems Inc.Inventors: Michael Antonell, Erik Cho Houge, Larry E. Plew, Catherine Vartuli, Jennifer Juszczak
-
Publication number: 20030219916Abstract: A semiconductor manufacturing automation method for analyzing a patterned feature formed on a semiconductor layer is disclosed. At least one patterned feature is scanned to generate an amplitude modulated waveform signal of the line and neighboring space characteristics. Signal processing is automatically performed on this waveform by an in-line computational source to extract known patterned features based on the profile of the amplitude modulated waveform signal. The extracted waveform segments are subjected to known geometric shapes to determine if the waveform indicates a normal or abnormal patterned feature on a semiconductor layer.Type: ApplicationFiled: May 24, 2002Publication date: November 27, 2003Inventors: Erik Cho Houge, Scott Jessen, John Martin McIntosh, Catherine Vartuli, Fred Anthony Stevie
-
Publication number: 20030193022Abstract: A method and apparatus used to calibrate high-resolution electron microscopes where a single standard provides multiple samples, each having a different atomic structure, permits rapid accurate calibration of the entire range of magnifications. The different atomic structure dimensions possess known reference measurement data. The S/TEM is adjusted to focus onto the crystal lattice structure of each sample in a selected sequence. Measurements of these lattice spacings are compared to known dimensions. If S/TEM measurements do not agree with the lattice spacing dimensions, the S/TEM magnification is adjusted to reflect known dimensions. Typical standard exchange and associated processing steps are eliminated by the use of the single standard comprising of a plurality of samples.Type: ApplicationFiled: April 12, 2002Publication date: October 16, 2003Inventors: Erik Cho Houge, Catherine Vartuli, John Martin Mclntosh, Fred Anthony Stevie
-
Patent number: 6633032Abstract: The present invention relates to a device for testing particles for composition and concentration. The device includes a particle counter, a collector screen, and a mass spectrometer. In one embodiment, the collector screen is positioned to receive particles received by the particle counter, and the mass spectrometer is positioned to receive counted particles retained on the collector screen.Type: GrantFiled: November 30, 2000Date of Patent: October 14, 2003Assignee: Agere Systems Inc.Inventors: Erik Cho Houge, John Martin McIntosh, Fred Anthony Stevie, Steven Barry Valle, Catherine Vartuli
-
Patent number: 6627885Abstract: The present invention provides a method of forming a dynamic template with a focused beam. The method includes forming a desired template that represents a desired image, forming an actual template that represents an actual image, such as a photolithographic mask or a semiconductor device feature, and comparing the desired template to the actual template to yield a deviation template. In one embodiment the deviation template is formed by subtracting the actual template from the desired template.Type: GrantFiled: August 3, 2000Date of Patent: September 30, 2003Assignee: Agere Systems Inc.Inventors: John M. McIntosh, Erik C. Houge, Fred A. Stevie, Catherine Vartuli, Scott Jessen
-
Patent number: 6606371Abstract: A reflective lens with at least one curved surface formed of polycrystalline material. In one embodiment, a lens structure includes a substrate having a surface of predetermined curvature and a film formed along a surface of the substrate with multiple individual members each having at least one similar orientation relative to the portion of the substrate surface adjacent the member such that collectively the members provide predictable angles for diffraction of x-rays generated from a common source. A system is also provided for performing an operation with x-rays. In one embodiment, a system includes a source for generating the x-rays, a polycrystalline surface region having crystal spacing suitable for reflecting a plurality of x-rays at the same Bragg angle along the region, and transmitting the reflected x-rays to a reference position.Type: GrantFiled: December 19, 2000Date of Patent: August 12, 2003Assignee: Agere Systems Inc.Inventors: Michael Antonell, Erik Cho Houge, John Martin McIntosh, Larry E. Plew, Catherine Vartuli
-
Patent number: 6603119Abstract: The present invention provides a method of calibrating an analytical tool. The method, in a illustrative embodiment, includes preparing a calibration standard having a known concentration of an element and obtaining a portion of the calibration standard with a focused beam, wherein the calibration standard is representative of the concentration. The portion of the calibration standard is then used to calibrate an analytical tool.Type: GrantFiled: May 9, 2000Date of Patent: August 5, 2003Assignee: Agere Systems Inc.Inventors: Lucille A. Giannuzzi, Frederick A. Stevie, Catherine Vartuli
-
Publication number: 20030107117Abstract: A manufacturing method using a modular substrate-based processing scheme for producing semiconductor devices, provides multiple modular processing units which may be arranged together to form any of various cohesive processing units or individually or sequentially processed through standard semiconductor processing equipment. The cohesive processing units are processed unitarily providing for multiple modular processing units to be processed simultaneously. The modular processing units may be formed of a thick semiconductor substrate or a semiconductor substrate mounted on a further substrate such as a ceramic material. The modular processing units may each contain ribs, grooves, posts or other features to aid in handling and placement of the individual units.Type: ApplicationFiled: November 25, 2002Publication date: June 12, 2003Applicant: Agere Systems Inc.Inventors: Michael Antonell, Erik Cho Houge, Nitin Patel, Larry E. Plew, Catherine Vartuli
-
Patent number: 6577970Abstract: The present invention provides a method of determining a crystallographic quality of a material located on a substrate. The method includes determining a set of crystallographic solutions for an unknown crystallographic orientation, and subsequently comparing the set of crystallographic solutions to adjacent known crystallographic orientations to determine the unknown crystallographic orientation. In a preferred embodiment, the set of crystallographic solutions may be a rank of crystallographic solutions which may represent the most probable crystallographic orientations. The rank of crystallographic solutions, in an alternative embodiment, may be represented by a vote, a fit and a confidence index.Type: GrantFiled: March 8, 2001Date of Patent: June 10, 2003Assignee: Agere Systems Inc.Inventors: Erik C. Houge, John M. McIntosh, Larry E. Plew, Fred A. Stevie, Catherine Vartuli
-
Patent number: 6569690Abstract: Method for fabricating a structure. According to an exemplary embodiment, a structure is made by forming a layer of removable material with a first surface spaced a part from a second surface. The first surface is formed along a first region from which the material is removable. The first surface is altered by removal of material from the layer. Removed material from the first surface is monitored to detect fluctuations in a variable of composition in the layer, and removal of material from the first surface is terminated when the composition of monitored material meets a predetermined criterion. In an alternate embodiment a variable characteristic is imparted to a layer of material as a function of layer thickness and an operation is performed on the layer resulting in removal of material. Samples of removed material are monitored for variation in the characteristic and the operation is modified when a variation conforms with a criterion.Type: GrantFiled: August 31, 2000Date of Patent: May 27, 2003Assignee: Agere Systems Guardian CorpInventors: Erik Cho Houge, Isik C. Kizilyalli, John Martin McIntosh, Fred Anthony Stevie, Catherine Vartuli
-
Publication number: 20030063967Abstract: A method and apparatus for minimizing the surface contamination of semiconductor wafers (11) during the semiconductor device manufacturing process. Semiconductor wafers (11) are stored in a storage cassette (12) with their face sides (17) facing downward and their back sides (16) facing upward. Particulate contamination present on the back sides of the wafers is thereby secured to the wafers by the force of gravity, and the faces of the wafers are shielded from falling debris. An automated wafer handling device (19) is provided with a rotary joint (22) to accomplish the wafer flipping motion before inserting a wafer into a cassette and after removing the wafer from the cassette.Type: ApplicationFiled: September 28, 2001Publication date: April 3, 2003Inventors: Michael Antonell, Erik Cho Houge, Larry E. Plew, Catherine Vartuli, Jennifer Juszczak
-
Patent number: 6534851Abstract: A modular substrate-based processing scheme for producing semiconductor devices provides multiple modular processing units which may be arranged together to form any of various cohesive processing units or they may be individually or sequentially processed through standard semiconductor processing equipment. The cohesive processing units are processed unitarily providing for multiple modular processing units to be processed simultaneously. The modular processing units may be formed of a thick semiconductor substrate or a semiconductor substrate mounted on a further substrate such as a ceramic material. The modular processing units may each contain ribs, grooves, posts or other features to aid in handling and placement of the individual units.Type: GrantFiled: August 21, 2000Date of Patent: March 18, 2003Assignee: Agere Systems, Inc.Inventors: Michael Antonell, Erik Cho Houge, Nitin Patel, Larry E. Plew, Catherine Vartuli
-
Patent number: 6519543Abstract: The present invention provides a method of calibrating an analytical tool. The method, in a illustrative embodiment, includes determining a concentration of an element located within a known matrix, obtaining a calibration standard of the known matrix with a polishing process, the calibration standard being representative of the concentration, and obtaining a detection limit of an analytical tool with respect to the concentration. Furthermore, secondary ion mass spectrometry may be used to determine the concentration of the element within the known matrix.Type: GrantFiled: May 9, 2000Date of Patent: February 11, 2003Assignee: Agere Systems Inc.Inventors: Lucille A. Giannuzzi, Frederick A. Stevie, Catherine Vartuli
-
Publication number: 20020131631Abstract: The present invention provides a method for detecting defects in a material and a system for accomplishing the same. The method includes obtaining an image of at least a portion of a material's surface and converting the image into an intensity profile. The method further includes determining a defect in the material's surface from the intensity profile. In one exemplary embodiment, the image is an electron image obtained using a scanning electron microscope. The method may further be used to determine a defect density in the material's surface.Type: ApplicationFiled: March 15, 2001Publication date: September 19, 2002Inventors: Erik C. Houge, Catherine Vartuli, Mike Antonell, Pam Cavanagh, Hui Ma
-
Publication number: 20020128789Abstract: The present invention provides a method of determining a crystallographic quality of a material located on a substrate. The method includes determining a set of crystallographic solutions for an unknown crystallographic orientation, and subsequently comparing the set of crystallographic solutions to adjacent known crystallographic orientations to determine the unknown crystallographic orientation. In a preferred embodiment, the set of crystallographic solutions may be a rank of crystallographic solutions which may represent the most probable crystallographic orientations. The rank of crystallographic solutions, in an alternative embodiment, may be represented by a vote, a fit and a confidence index.Type: ApplicationFiled: March 8, 2001Publication date: September 12, 2002Inventors: Erik C. Houge, John M. McIntosh, Larry E. Plew, Fred A. Stevie, Catherine Vartuli