Abstract: A semiconductor memory cell, a method for fabricating it and a semiconductor memory device. A phase change material region of a storage element of the semiconductor memory cell has been or is formed as a lining region of a wall region of a contact recess which passes all the way through an insulation region between a first electrode device and a second electrode device. Furthermore, the space or region of the contact recess which is not taken up by the material region of the storage element has been or is made substantially electrically insulating.

Abstract: A method for fabricating a solid electrolyte memory device comprises a plurality of solid electrolyte memory cells, the solid electrolyte memory cells sharing a common continuous solid electrolyte layer comprising solid electrolyte cell areas and solid electrolyte inter-cell areas, the method comprising the process of introducing mobile ion solubility reducing material or mobile ion mobility reducing material into the solid electrolyte inter-cell areas.

Abstract: A ferroelectric memory arrangement having memory cells, in each of which a vertical ferroelectric storage capacitor, which includes vertical electrodes and a ferroelectric dielectric between the vertical electrodes, is connected to a select transistor, the ferroelectric dielectric a plurality of ferroelectric layers, between each of which is arranged an insulating separating layer.

Abstract: A method is describe for fabricating memory components including memory cells based on an active material of an active layer, the phase state of which can be changed and which is enclosed between a bottom electrode and a top electrode. To reduce the current intensity of the programming current and the erase current required for programming and erasing of the memory element and therefore the quantity of heat which is required to change the phase state, a nanoporous aluminium oxide layer is used as a mask during the production of the active layer or the interface with the electrodes. The nanoporous aluminium oxide layer can be used as a positive mask, as a negative mask, or used directly as an insulating current aperture. The contact surface between electrode and active layer can be set in virtually any desired form by varying the process parameters of the aluminium oxide mask.

Abstract: According to the invention CBRAM cell is provided exhibiting a resistive switching effect offering the possibility to store multiple memory states in one cell by programming said memory cell to different resistance levels including at least a first memory state with a high resistance level representing a low-conductivity state of the memory cell and one memory state with a low resistance level representing a high-conductivity state of the memory cell, wherein the resistive switching effect is substantially based on a variation of the concentration of the metallic material incorporated or deposited in the matrix host material.

Abstract: One aspect of the invention relates to a semiconductor arrangement having at least one nonvolatile memory cell which has a first electrode comprising at least two layers; and having an organic material, the organic material forming a compound with that layer of the first electrode which is in direct contact. One aspect of the invention furthermore relates to a method for producing the nonvolatile memory cell, a semiconductor arrangement having a plurality of memory cells according to the invention, and a method for producing the same.

Abstract: The invention refers to an improved programmable structure, an improved memory, an improved display and an improved method for reading data from a memory cell. More particularly, embodiments of the invention provide a programmable structure and a memory, whereby a programmed state of the programmable structure and a programmed state of a memory cell of the memory can be read out with a simple method. According a further aspect of the present invention, the stored data of the programmable structure and the stored data of the memory device can be read out according an improved method.

Abstract: When fabricating a memory cell with an organic storage layer which stores a digital information item, processing of polycrystalline and monocrystalline semiconductor structures in which high temperatures are employed is concluded prior to application of the organic storage layer.

Abstract: Semiconductor memory cell and also a corresponding fabrication method are described, in which a first or bottom electrode device of the memory element of the semiconductor memory cell according to the invention and the gate electrode device of the underlying field effect transistor as selection transistor of the semiconductor memory cell are formed as the same material region or with a common material region.

Abstract: Method for fabricating an integrated device, comprising the step of providing a substrate, which includes an electrode element, and a step of providing a solid electrolyte element coupled to the electrode element. The solid electrolyte element is provided in a crystalline state and in conjunction with electrode element such to form a programmable resistance element. The method furthermore comprises a heating process, after providing the solid electrolyte element.

Abstract: The object of providing a method for manufacturing a phase change memory, as well as a phase change memory so as to better harmonize the contrary requirements for the phase change material is solved by the present invention by a method for manufacturing a phase change memory comprising at least one resistively switching memory cell, wherein the phase change material layer contains a switching active GaxGeyInzSb1-x-y-z material compound that is doped with nitrogen or oxygen. A phase change memory according to the present invention comprising a phase change material layer with the chemical composition GaxGeyInzSb1-x-y-z:N/:O is adapted to be operated with lower currents, has a higher writing rate, and is characterized by improved data storage at increased temperatures.

Abstract: An integrated semiconductor memory includes a storage medium (6) arranged between two electrodes (10, 20), which storage medium may be a phase change medium, for example. The storage medium (6) can be put into a first state or a second state by means of an electric current, as a result of which an item of information can be stored. According to embodiments of the invention, a layer plane (L) is provided in which impurity particles made from a material (4) are embedded, as a result of which the current density in the storage medium is locally increased and the programming current required for reprogramming is reduced. As a result, the current consumption of memory elements containing a phase change medium is reduced, so that for the first time they can be embodied with minimal feature size, together with other components such as transistors, and integrated into a single semiconductor circuit and no longer have to be arranged in separate subcircuits.

Abstract: The storage layer (6) is in each case present above a region in which the channel region (3) adjoins a source/drain region (2) and is in each case interrupted above an intervening middle part of the channel region (3). The storage layer (6) is formed by material of the gate dielectric (4) and contains silicon or germanium nanocrystals or nanodots introduced through ion implantation. The gate electrode (5) is widened at the flanks by electrically conductive spacers (7).

Abstract: A solid electrolyte memory element comprising an inert cathode electrode, a reactive anode electrode and a solid electrolyte layer disposed between the inert cathode electrode and the reactive anode electrode, wherein the solid electrolyte layer comprises a solid electrolyte matrix having defect sites.

Abstract: A method for manufacturing an electrolyte material layer with a chalcogenide material incorporated or deposited therein for use in semiconductor memory devices, in particular resistively-switching memory devices or components. The method comprises the steps of producing a semiconductor substrate, depositing a binary chalcogenide layer onto the semiconductor substrate, depositing a sulphur-containing layer onto the binary chalcogenide layer, and creating a ternary chalcogenide layer comprising at least two different chalcogenide compounds ASexSy. One component A of the chalcogenide compounds ASexSy comprises materials of the IV elements main group, e.g., Ge, Si, or of a transition metal, preferably of the group consisting of Zn, Cd, Hg, or a combination thereof.

Abstract: An electrical switching device comprises a switching element and a heating device for heating the switching element. The switching element comprises a first electrode, a second electrode, and an electrolyte layer arranged between and contact-connected to the first and second electrode. The switching element is configured to establish a conducting path between the first and second electrodes via the electrolyte layer by conduction elements having diffused from the first electrode into the electrolyte layer.

Abstract: A semiconductor memory device suitable for use in a memory cell array includes a solid electrolyte memory cell including: a first electrode device, a second electrode device, and a solid electrolyte material region between the first and second electrode devices. The solid electrolyte material region is materially cohesive, and the second electrode device is materially cohesive.

Abstract: A nonvolatile integrated semiconductor memory has an arrangement of layers with a tunnel barrier layer and a charge-storing level. The charge-storing level has a dielectric material which stores scattered in charge carriers in a spatially fixed position. The tunnel barrier layer has a material through which high-energy charge carriers can tunnel. At least one interface surface of the charge-storing level has a greater microscopic roughness than the interface surface of the tunnel barrier layer, which is remote from the charge-storing level. The charge-storing level has a greater layer thickness in first regions than in second regions. This produces a relatively identical distribution and localization of positive and negative charge carriers in the lateral direction. The charge carriers which are scattered into the charge-storing level, therefore, recombine completely, so that the risk of unforeseen data loss during long-term operation of nonvolatile memories is reduced.

Abstract: A memory cell field with an integrated arrangement of solid body electrolyte memory cells, and in particular of CBRAM solid body electrolyte memory cells with 1T1R architecture, wherein the solid body electrolyte memory cells each comprise a layer stack that comprises at least a bottom and a top electroconductive, in particular metal layer and a layer of solid body electrolyte material or ion conductor material, respectively, positioned therebetween, and wherein each solid body electrolyte memory cell can be controlled via a word line, a bit line, and a plate line by means of a selection transistor, wherein at least a number of solid body electrolyte memory cells in the memory cell field have a common plate electrode or are connected to a common plate line, respectively.

Abstract: A non-volatile, resistively switching memory cell is disclosed. In one embodiment, the memory cell has a first electrode, a second electrode and a solid electrolyte, which is arranged such that it makes contact between the electrodes, and is composed of an amorphous or partially amorphous, non-oxidic matrix and a metal which is distributed in the amorphous or partially amorphous, non-oxidic matrix and whose cations migrate to the cathode in the amorphous or partially amorphous, non-oxidic matrix under the influence of an electrical voltage, wherein the solid electrolyte contains one or more further metallic materials for stabilization of the amorphous state of the matrix.