Patents by Inventor Cay-Uwe Pinnow

Cay-Uwe Pinnow has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060091476
    Abstract: A method which makes it possible to define in a patterning layer openings having a first dimension that is substantially less than the feature size that can be obtained lithographically includes applying a sacrificial layer made of a material that is different from that of the patterning layer in a predetermined layer thickness on the patterning layer. Afterward, a photoresist layer is applied on the surface of the sacrificial layer, and an opening having a second dimension is defined lithographically in the photoresist layer. Afterward, an etching angle is set in a manner dependent on the layer thickness of the sacrificial layer and also the first and second dimensions, and the sacrificial layer is etched at the etching angle set. Afterward, the patterning layer is etched, the sacrificial layer is removed and a filling material is introduced into the opening produced in the patterning layer.
    Type: Application
    Filed: October 26, 2005
    Publication date: May 4, 2006
    Inventors: Cay-Uwe Pinnow, Thomas Happ, Michael Kund, Gerhard Mueller
  • Publication number: 20060071244
    Abstract: The invention relates to a method for operating a switching or amplifier device (11, 111), and to a switching or amplifier device (11, 111) comprising: an active material (13, 113) adapted to be placed in a more or less conductive state by means of appropriate switching processes; and at least three electrodes or contacts (12a, 12b, 12c).
    Type: Application
    Filed: July 25, 2005
    Publication date: April 6, 2006
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Martin Gutsche, Cay-Uwe Pinnow
  • Publication number: 20060049390
    Abstract: A nonvolatile, resistively switching memory cell includes a layer arranged between a first electrode and a second electrode. The layer includes one or more chalcogenide compound(s) selected from the group consisting of CuInS, CuInSe, CdInS, CdInSe, ZnInS, MnInS, MnZnInS, ZnInSe, InS, InSSe and InSe, with alkali metal or alkaline-earth metal ions contained in the layer of the chalcogenide compound(s).
    Type: Application
    Filed: August 23, 2005
    Publication date: March 9, 2006
    Inventors: Klaus Ufert, Cay-Uwe Pinnow, Thomas Happ
  • Publication number: 20060049440
    Abstract: A ferroelectric memory arrangement having memory cells, in each of which a vertical ferroelectric storage capacitor, which includes vertical electrodes and a ferroelectric dielectric between the vertical electrodes, is connected to a select transistor, the ferroelectric dielectric a plurality of ferroelectric layers, between each of which is arranged an insulating separating layer.
    Type: Application
    Filed: August 31, 2005
    Publication date: March 9, 2006
    Inventors: Rainer Bruchhaus, Martin Gutsche, Cay-Uwe Pinnow
  • Publication number: 20060046379
    Abstract: A method is describe for fabricating memory components including memory cells based on an active material of an active layer, the phase state of which can be changed and which is enclosed between a bottom electrode and a top electrode. To reduce the current intensity of the programming current and the erase current required for programming and erasing of the memory element and therefore the quantity of heat which is required to change the phase state, a nanoporous aluminium oxide layer is used as a mask during the production of the active layer or the interface with the electrodes. The nanoporous aluminium oxide layer can be used as a positive mask, as a negative mask, or used directly as an insulating current aperture. The contact surface between electrode and active layer can be set in virtually any desired form by varying the process parameters of the aluminium oxide mask.
    Type: Application
    Filed: August 24, 2005
    Publication date: March 2, 2006
    Inventors: Ralf Symanczyk, Cay-Uwe Pinnow, Thomas Happ
  • Publication number: 20060043354
    Abstract: A chalcogenide layer includes a composition of compounds having the formula MmX1-m, where M denotes one or more elements selected from the group consisting of group IVb elements of the periodic system, group Vb elements of the periodic system and transition metals, X denotes one or more elements selected from the group consisting of S, Se and Te, and m has a value of between 0 and 1. The chalcogenide layer further includes an oxygen or nitrogen content in the range from 0.001 atomic % to 75 atomic %.
    Type: Application
    Filed: August 30, 2005
    Publication date: March 2, 2006
    Inventors: Cay-Uwe Pinnow, Thomas Happ
  • Publication number: 20060001000
    Abstract: A method for producing a solid electrolyte material region for a memory element of a solid electrolyte memory cell. A first material is formed in substantially pure form. A thermal treatment is carried out in the presence of at least one second material, and the chalcogenide material of the solid electrolyte material region thereby being produced.
    Type: Application
    Filed: June 16, 2005
    Publication date: January 5, 2006
    Inventors: Cay-Uwe Pinnow, Klaus-Dieter Ufert
  • Publication number: 20050286211
    Abstract: The present invention relates to a switching element for reversible switching between an electrically insulating OFF state and an electrically conductive ON state, having two electrodes, namely a reactive electrode and an inert electrode, and also a solid electrolyte arranged between the two electrodes, which is characterized by the fact that the electrical conductivity of the solid electrolyte increases as the temperature thereof rises, but essentially no longer increases below a critical decomposition temperature of the solid electrolyte.
    Type: Application
    Filed: May 18, 2005
    Publication date: December 29, 2005
    Inventors: Cay-Uwe Pinnow, Klaus-Dieter Ufert
  • Publication number: 20050250281
    Abstract: The present invention relates to a reproducible conditioning during the manufacturing of a resistively switching CBRAM memory cell comprising a first electrode and a second electrode with an active material positioned therebetween. The active material is adapted to be placed in a more or less electroconductive state by means of electrochemical switching processes. A CBRAM memory cell manufactured pursuant to the method according to the invention has, due to the improved conditioning, more reliable and more distinctly evaluable electrical switching properties. Moreover, no more forming step is necessary with the method according to the present invention.
    Type: Application
    Filed: April 25, 2005
    Publication date: November 10, 2005
    Applicant: Infineon Technologies AG
    Inventors: Klaus Ufert, Cay-Uwe Pinnow
  • Publication number: 20050212037
    Abstract: A semiconductor memory cell, a method for fabricating it and a semiconductor memory device. A phase change material region of a storage element of the semiconductor memory cell has been or is formed as a lining region of a wall region of a contact recess which passes all the way through an insulation region between a first electrode device and a second electrode device. Furthermore, the space or region of the contact recess which is not taken up by the material region of the storage element has been or is made substantially electrically insulating.
    Type: Application
    Filed: March 9, 2005
    Publication date: September 29, 2005
    Inventors: Cay-Uwe Pinnow, Klaus-Dieter Ufert
  • Publication number: 20050201143
    Abstract: Semiconductor memory cell and also a corresponding fabrication method are described, in which a first or bottom electrode device of the memory element of the semiconductor memory cell according to the invention and the gate electrode device of the underlying field effect transistor as selection transistor of the semiconductor memory cell are formed as the same material region or with a common material region.
    Type: Application
    Filed: March 9, 2005
    Publication date: September 15, 2005
    Inventors: Cay-Uwe Pinnow, Ralf Symanczyk
  • Publication number: 20050180189
    Abstract: The invention relates to a memory device electrode, in particular for a resistively switching memory device, wherein the surface of the electrode is provided with a structure, in particular comprises one or a plurality of shoulders or projections, respectively. Furthermore, the invention relates to a memory cell comprising at least one such electrode, a memory device, as well as a method for manufacturing a memory device electrode.
    Type: Application
    Filed: February 16, 2005
    Publication date: August 18, 2005
    Applicant: Infineon Technologies AG
    Inventors: Thomas Happ, Cay-Uwe Pinnow, Michael Kund
  • Publication number: 20050067634
    Abstract: A nonvolatile integrated semiconductor memory has an arrangement of layers with a tunnel barrier layer and a charge-storing level. The charge-storing level has a dielectric material which stores scattered in charge carriers in a spatially fixed position. The tunnel barrier layer has a material through which high-energy charge carriers can tunnel. At least one interface surface of the charge-storing level has a greater microscopic roughness than the interface surface of the tunnel barrier layer, which is remote from the charge-storing level. The charge-storing level has a greater layer thickness in first regions than in second regions. This produces a relatively identical distribution and localization of positive and negative charge carriers in the lateral direction. The charge carriers which are scattered into the charge-storing level, therefore, recombine completely, so that the risk of unforeseen data loss during long-term operation of nonvolatile memories is reduced.
    Type: Application
    Filed: September 28, 2004
    Publication date: March 31, 2005
    Inventors: Cay-Uwe Pinnow, Martin Gutsche, Harald Seidl, Thomas Happ
  • Publication number: 20050067659
    Abstract: The storage layer (6) is in each case present above a region in which the channel region (3) adjoins a source/drain region (2) and is in each case interrupted above an intervening middle part of the channel region (3). The storage layer (6) is formed by material of the gate dielectric (4) and contains silicon or germanium nanocrystals or nanodots introduced through ion implantation. The gate electrode (5) is widened at the flanks by electrically conductive spacers (7).
    Type: Application
    Filed: August 11, 2004
    Publication date: March 31, 2005
    Inventors: Martin Gutsche, Josef Willer, Cay-Uwe Pinnow, Ralf Symanczyk