Patents by Inventor Ce Ning

Ce Ning has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11133363
    Abstract: The present discloses an array substrate and a manufacturing method thereof, and a display device. The array substrate includes a first transistor and a second transistor. The first transistor includes a first active layer, a first gate, a first source and a first drain. The second transistor includes a second active layer, a second gate, a second source and a second drain. An orthographic projection of the second source on the base substrate and an orthographic projection of the second drain on the base substrate at least partially overlap. One of the second source and the second drain is in the same layer as and made from the same material as the first gate. The first source and the first drain are in the same layer as and made from the same material as the other of the second source and the second drain.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: September 28, 2021
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Ke Wang, Xinhong Lu, Hehe Hu, Wei Yang, Ce Ning
  • Patent number: 11092866
    Abstract: The present disclosure provides a display panel and a manufacturing method thereof, a driving method and a display device. The display panel includes: a base substrate and a thin film transistor on a surface of the base substrate. The thin film transistor includes: a gate, and a source and a drain arranged along a first direction, and a first passivation layer covering the gate, the source and the drain. a space region in which liquid crystal molecules are filled is formed in the first passivation layer. The space region is between the source and the drain. The source and the drain are configured to control rotation of the liquid crystal molecules.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: August 17, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Hehe Hu, Xiaochen Ma, Guangcai Yuan, Ce Ning, Xin Gu
  • Publication number: 20210229088
    Abstract: A microfluidic channel and a preparation method and an operation method thereof. The microfluidic channel includes: a channel structure, including a channel for a liquid sample to flow through and a channel wall surrounding the channel. The channel wall includes an electrolyte layer made of an electrolyte material; and a control electrode layer, at a side of the electrolyte layer away from the channel. The control electrode layer overlaps with the electrolyte layer with respect to the channel.
    Type: Application
    Filed: March 11, 2019
    Publication date: July 29, 2021
    Inventors: Xiaochen MA, Guangcai YUAN, Ce NING, Zhengliang LI
  • Publication number: 20210229977
    Abstract: A micro-nano channel structure, a method for manufacturing the micro-nano channel structure, a sensor, a method for manufacturing the sensor, and a microfluidic device are provided by the embodiments of the present disclosure. The micro-nano channel structure includes: a base substrate; a base layer, on the base substrate and including a plurality of protrusions; and a channel wall layer, on a side of the plurality of the protrusions away from the base substrate, and the channel wall layer has a micro-nano channel; a recessed portion is provided between adjacent protrusions of the plurality of the protrusions, and an orthographic projection of the micro-nano channel on the base substrate is located within an orthographic projection of the recessed portion on the base substrate.
    Type: Application
    Filed: April 3, 2019
    Publication date: July 29, 2021
    Inventors: Xiaochen MA, Guangcai YUAN, Ce NING, Xin GU, Xiao ZHANG Xiao ZHANG, Chao LI
  • Publication number: 20210220824
    Abstract: The present disclosure relates to a micro-channel device. The micro-channel device may include a micro-channel structure and a semiconductor junction. The micro-channel structure may include a base layer, a plurality of rails distributed on the base layer at intervals, and a cover layer comprising a plurality of columns. The cover layer and the base layer are configured to form a plurality of micro-channels. The semiconductor junction may include a P-type semiconductor layer, an intrinsic semiconductor layer and a N-type semiconductor layer stacked in a first direction.
    Type: Application
    Filed: April 16, 2019
    Publication date: July 22, 2021
    Applicant: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Ce Ning, Xiaochen Ma, Hehe Hu, Guangcai Yuan, Xin Gu
  • Publication number: 20210226064
    Abstract: Provided are a thin film transistor including: a base cushion layer having a recessed portion, base insulating layer, source-drain layer and active layer. The base insulating layer is located on a side of the base cushion layer where the recessed portion is located, and has a first and second partition walls that are spaced apart, and an orthographic projection region of a gap region between the first and second partition walls onto the base cushion layer is located at a region where the recessed portion is located; and both orthographic projection regions of the first and second partition walls onto the base cushion layer partially overlap with the recessed portion region; and both the source-drain layer and the active layer are located on the side of the base insulating layer away from the base cushion layer.
    Type: Application
    Filed: November 19, 2019
    Publication date: July 22, 2021
    Inventors: Xiaochen Ma, Guangcai Yuan, Ce Ning, Xin Gu, Hehe Hu
  • Publication number: 20210225893
    Abstract: A method of manufacturing an array substrate includes: forming a first semiconductor pattern and a first insulating layer group sequentially on a base substrate; forming a second semiconductor pattern and a second insulating layer group sequentially on the first insulating layer group; forming two first via holes in the first insulating layer group and the second insulating layer group to expose the first semiconductor pattern, annealing the exposed first semiconductor pattern and then removing an oxide layer on a surface of the first semiconductor pattern; forming connecting wires in the first via holes; forming second via holes in the second insulating layer group to expose the second semiconductor pattern, and forming a first source electrode and a first drain electrode in the second via holes such that the first source electrode or the first drain electrode covers and is connected to one of the connecting wires.
    Type: Application
    Filed: December 6, 2019
    Publication date: July 22, 2021
    Inventors: Wei YANG, Guangcai YUAN, Ce NING, Xinhong LU, Tianmin ZHOU, Xin YANG
  • Patent number: 11024657
    Abstract: The present disclosure provides a transistor, an array substrate and a method of manufacturing the array substrate, and a display device. The method of manufacturing the array substrate comprises: depositing a plurality of silicon oxide layers on an active layer of a transistor; and depositing a silicon oxynitride layer over the plurality of silicon oxide layers.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: June 1, 2021
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Zhengliang Li, Ce Ning, Song Liu, Wenlin Zhang, Xuefei Sun
  • Publication number: 20210129140
    Abstract: A microfluidic channel structure and a fabrication method thereof, a microfluidic detecting device and a detecting method thereof are disclosed. The microfluidic channel structure includes a support portion; a foundation portion, provided on the support portion and including a first foundation and a second foundation spaced apart from each other; and a channel defining portion, provided on a side of the foundation portion that is away from the support portion and including a first channel layer and a second channel layer, the first channel layer covering the first foundation and the second channel layer covering the second foundation have a gap therebtween to define a microfluidic channel; and the first channel layer and the second channel layer are made of a same material.
    Type: Application
    Filed: September 24, 2019
    Publication date: May 6, 2021
    Inventors: Xiaochen MA, Guangcai YUAN, Ce NING, Xin GU, Hehe HU
  • Publication number: 20210134900
    Abstract: A light emitting substrate and a manufacturing method thereof, and an electronic device are provided, the method includes: forming a pixel definition layer by a patterning process using a first mask, in which the pixel definition layer includes an opening and a partition portion defining the opening; forming a first electrode, in which the first electrode includes a first portion covering at least a part of the partition portion and includes a second portion in the opening; and forming an auxiliary electrode by a patterning process using the first mask, in which the auxiliary electrode is electrically connected with the first electrode, and the auxiliary electrode is on the partition portion.
    Type: Application
    Filed: March 29, 2019
    Publication date: May 6, 2021
    Inventors: Mingxiao JIANG, Weifeng ZHOU, Ce NING
  • Publication number: 20210063793
    Abstract: The present disclosure provides a display panel and a manufacturing method thereof, a driving method and a display device. The display panel includes: a base substrate and a thin film transistor on a surface of the base substrate. The thin film transistor includes: a gate, and a source and a drain arranged along a first direction, and a first passivation layer covering the gate, the source and the drain. a space region in which liquid crystal molecules are filled is formed in the first passivation layer. The space region is between the source and the drain. The source and the drain are configured to control rotation of the liquid crystal molecules.
    Type: Application
    Filed: July 18, 2019
    Publication date: March 4, 2021
    Inventors: Hehe HU, Xiaochen MA, Guangcai YUAN, Ce NING, Xin GU
  • Patent number: 10916662
    Abstract: An oxide thin film transistor, an array substrate, and preparation methods thereof are disclosed. The method for preparing an oxide thin film transistor comprises a step of forming a pattern comprising an oxide semiconductor active layer on a substrate, wherein the step comprises: forming an amorphous oxide semiconductor thin film on the substrate; performing an excimer laser annealing, at least at a position in the amorphous oxide semiconductor thin film corresponding to a channel region of oxide semiconductor active layer to be formed, such that the amorphous oxide semiconductor material at the laser-annealed position is crystallized, to form a crystalline oxide semiconductor material; and forming the pattern comprising the oxide semiconductor active layer.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: February 9, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Feng Guan, Guangcai Yuan, Zhi Wang, Chen Xu, Qi Yao, Zhanfeng Cao, Ce Ning, Woobong Lee, Lei Chen
  • Patent number: 10889504
    Abstract: An oxide semiconductor composition for use in thin film transistors includes indium oxide, zinc oxide, and an oxide including a doping element of scandium, such as scandium oxide. A molar percentage of the indium oxide can be larger than approximately 50%. The oxide semiconductor composition can have a formula of In2Sc2ZnO7. Manufacturing of the oxide semiconductor composition can include: mixing indium oxide powder, scandium oxide powder, and zinc oxide powder to thereby obtain an oxide shaped object; and sintering the oxide shaped object to form the oxide semiconductor composition. A thin-film transistor for use in a semiconductor device, such as a display apparatus, can include the oxide semiconductor composition, and can thereby have improved mobility of the oxide semiconductor due to the reduced oxygen vacancy therein.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: January 12, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Wenlin Zhang, Ce Ning, Hehe Hu, Zhengliang Li
  • Patent number: 10795478
    Abstract: Provided are an array substrate and preparation method therefor, and a display apparatus. The array substrate includes: a substrate, the substrate having a first TFT region, a touch control region and a second TFT region; a photosensitive PN junction, the photosensitive PN junction being provided in the touch control region; a first thin-film transistor, provided in the first TFT region, and electrically connected to the photosensitive PN junction; and a second thin-film transistor, provided in the second TFT region, and electrically connected to a pixel electrode.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: October 6, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Wenlin Zhang, Wei Yang, Ce Ning
  • Publication number: 20200286929
    Abstract: The present disclosure provides a transistor, an array substrate and a method of manufacturing the array substrate, and a display device. The method of manufacturing the array substrate comprises: depositing a plurality of silicon oxide layers on an active layer of a transistor; and depositing a silicon oxynitride layer over the plurality of silicon oxide layers.
    Type: Application
    Filed: April 2, 2018
    Publication date: September 10, 2020
    Inventors: Zhengliang LI, Ce NING, Song LIU, Wenlin ZHANG, Xuefei SUN
  • Publication number: 20200194553
    Abstract: The present application provides a TFT, a manufacturing method thereof, and a sensor. The TFT includes a substrate, and a source, a drain and an active layer on the substrate. The active layer includes a microchannel, and the thin film transistor is configured to detect a sample in the microchannel. When a sample to be detected enters the microchannel, the electron distribution in the active layer would be affected, which causes fluctuations in the TFT characteristics. By detecting such fluctuations, detecting the composition and property of the liquid to be detected may be achieved. Moreover, by virtue of the microchannel, the sample may be precisely controlled. The impact of the external environment may be reduced and the detection accuracy can be enhanced. Continuous monitoring instead of one-time detection of the sample may be achieved and the sample detection efficiency may be improved.
    Type: Application
    Filed: July 24, 2019
    Publication date: June 18, 2020
    Inventors: Xiaochen MA, Guangcai YUAN, Ce NING, Hehe HU, Xin GU
  • Publication number: 20200185535
    Abstract: An oxide thin film transistor, an array substrate, and preparation methods thereof are disclosed. The method for preparing an oxide thin film transistor comprises a step of forming a pattern comprising an oxide semiconductor active layer on a substrate, wherein the step comprises: forming an amorphous oxide semiconductor thin film on the substrate; performing an excimer laser annealing, at least at a position in the amorphous oxide semiconductor thin film corresponding to a channel region of oxide semiconductor active layer to be formed, such that the amorphous oxide semiconductor material at the laser-annealed position is crystallized, to form a crystalline oxide semiconductor material; and forming the pattern comprising the oxide semiconductor active layer.
    Type: Application
    Filed: August 1, 2019
    Publication date: June 11, 2020
    Inventors: Feng Guan, Guangcai Yuan, Zhi Wang, Chen Xu, Qi Yao, Zhanfeng Cao, Ce Ning, Woobong Lee, Lei Chen
  • Patent number: 10629834
    Abstract: The present disclosure relates to the field of display, in particular to a thin film transistor, a method for preparing the same, and a display device. The thin film transistor of the present disclosure includes a gate electrode, a gate insulating layer, a semiconductor layer, a source electrode, a drain electrode, and a photoelectric conversion layer in contact with the gate electrode. The photoelectric conversion layer is configured to generate an induced potential in a light environment.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: April 21, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Song Liu, Yu Wen, Jianming Sun, Zhengliang Li, Xiaochen Ma, Hehe Hu, Wenlin Zhang, Jianhua Du, Ce Ning
  • Publication number: 20200119120
    Abstract: An array substrate includes a base substrate and a plurality of pixel units disposed on a base substrate, and at least one pixel unit includes a plurality of thin film transistors, a first electrode, and a second electrode. The plurality of thin film transistors include at least one first thin film transistor including a first active pattern, a first gate, a first source and a first drain. The first electrode is disposed in a same layer as the first active pattern, the first electrode is coupled to the first drain, and the second electrode is disposed in a same layer as the first gate. Orthographic projections of any two in a group consisting of the first electrode, the second electrode, and the first drain on the base substrate have an overlapping region.
    Type: Application
    Filed: December 12, 2019
    Publication date: April 16, 2020
    Inventors: Jing FENG, Dongsheng YIN, Ce NING, Jiushi WANG
  • Patent number: 10615284
    Abstract: The present disclosure provides a thin film transistor, a method for fabricating the same, a display substrate, and a display apparatus, and belongs to the field of display technology. The method includes: forming a metal oxide semiconductor pattern comprising first and second metal oxide semiconductor layers, the second metal oxide semiconductor layer being above the first metal oxide semiconductor layer; depositing a source-drain metal layer on the metal oxide semiconductor pattern; etching the source-drain metal layer and the second metal oxide semiconductor layer to form source and drain electrodes and an active layer of the thin film transistor. The active layer is obtained after removing the second metal oxide semiconductor layer between the source and drain electrodes using a first etchant, and the first etchant has a higher etching rate on the second metal oxide semiconductor layer than on the first metal oxide semiconductor layer.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: April 7, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Wei Yang, Ce Ning, Hehe Hu, Ke Wang