Abstract: A micro-nano channel structure, a method for manufacturing the micro-nano channel structure, a sensor, a method for manufacturing the sensor, and a microfluidic device are provided. The micro-nano channel structure includes: a base substrate; a base layer, on the base substrate and including a plurality of protrusions; a channel wall layer, on a side of the plurality of the protrusions away from the base substrate, the channel wall layer has a micro-nano channel; a recessed portion is provided between adjacent protrusions of the plurality of the protrusions, an orthographic projection of the micro-nano channel on the base substrate is located within an orthographic projection of the recessed portion on the base substrate. The micro-nano channels have a high resolution or an ultra-high resolution, and have different sizes and shapes.

Abstract: An array substrate includes a base substrate, a driving circuit layer, and a functional device layer which are sequentially stacked; the driving circuit layer is provided with first driving circuits, and each first driving circuit at least includes a driving transistor; and the driving circuit layer includes a first gate layer, a first gate insulation layer, a semiconductor layer, a second gate insulation layer, a second gate layer, an interlayer dielectric layer, and a source-drain metal layer which are sequentially stacked on one side of the base substrate.

Abstract: The present disclosure provides a display substrate, a display panel and a display apparatus. The display substrate includes a first base substrate; a plurality of gate lines and a plurality of data lines which are arranged on a side of the first base substrate; the plurality of gate lines and the plurality of data lines are arranged to be intersected with each other and insulated from each other; a planarization layer, arranged on a side of the gate lines and the data lines away from the first base substrate, and including a first via hole; and a supporting structure, arranged on a side of the planarization layer away from the first base substrate and filled into the first via hole; and in a direction perpendicular to the first base substrate, a height of the supporting structure is greater than a depth of the first via hole.

Abstract: A thin film transistor includes a gate electrode, an active layer, a gate insulating layer located between the gate electrode and the active layer, and a source electrode and a drain electrode electrically connected to the active layer. The active layer includes a channel layer and at least one channel protection layer; a material of each of the channel layer and the at least one channel protection layer is a metal oxide semiconductor material. The at least one channel protection layer is a crystallizing layer, and metal elements of the at least one channel protection layer include non-rare earth metal elements including In, Ga, Zn and Sn.

Abstract: A microfluidic channel backplane includes a base, and a plurality of microfluidic channels, a sample-adding channel and an enrichment channel that are disposed above the base. Each microfluidic channel of the plurality of microfluidic channels includes a first end and a second end. The sample-adding channel is communicated with first ends of the plurality of microfluidic channels. The enrichment channel includes a first enrichment sub-channel and a second enrichment sub-channel. The first enrichment sub-channel is communicated with second ends of the plurality of microfluidic channels, and one end of the second enrichment sub-channel is communicated with the first enrichment sub-channel.

Abstract: A display panel is disclosed. In the display panel, the second electrode is electrically connected to the first electrode through the first via hole, and a first support structure is provided in a region corresponding to the first via hole; and at least a part of the first support structure is located in the first via hole, and an orthographic projection of the first via hole on the base substrate at least partially overlaps with an orthographic projection of the gate line on the base substrate, the first support structure extends upward within the first via hole to an upper opening region of the first via hole, and a top of the first support structure is higher than the upper surface of the first interlayer insulating layer, a surface of the first support structure close to the second substrate is a curved surface.

Abstract: Provided is a substrate. The substrate includes a base substrate; and a plurality of sub-pixel structures arranged in an array on the base substrate, wherein the sub-pixel structure comprises: a thin film transistor disposed on the base substrate, the thin film transistor comprising a source and a drain; an insulating layer disposed on a side of the thin film transistor distal from the base substrate, a first via hole being formed in the insulating layer; a pixel electrode disposed on a side of the insulating layer distal from the base substrate, the pixel electrode being electrically connected to either the source or the drain through the first via hole; and a filling block disposed at the first via hole.

Abstract: A displaying base plate and a displaying device are provided by the present application, wherein the displaying base plate includes a substrate, and a first electrode layer disposed on one side of the substrate, wherein the first electrode layer includes a first electrode pattern; a first planarization layer disposed on one side of the first electrode layer that is away from the substrate, wherein the first planarization layer is provided with a through hole, and the through hole penetrates the first planarization layer, to expose the first electrode pattern; and a second electrode layer, a second planarization layer and a third electrode layer that are disposed in stack on one side of the first planarization layer that is away from the substrate.

Abstract: The present disclosure provides a thin film transistor, a GOA circuit and an array substrate, the thin film transistor comprising: a source electrode, including a source electrode wiring and a plurality of source electrode branches; a drain electrode, including a drain electrode wiring and a plurality of drain electrode branches; a gate; a semiconductor layer comprising a plurality of semiconductor branches; a plurality of source electrode branches, wherein the plurality of drain electrode branches are in contact with the plurality of semiconductor branches and are divided into a plurality of cells; the source electrode wiring and the drain electrode wiring are arranged in a parallel and spaced apart, and the number m of one of the source electrode wiring and the drain electrode wiring is an integer greater than or equal to 2, and the number n of the other is an integer greater than or equal to 1.

Abstract: An array substrate and a manufacturing method therefor, and a display apparatus are provided. The array substrate includes an underlay substrate, and at least one first transistor, at least one data line and at least one pixel electrode disposed on the underlay substrate. The at least one first transistor includes a first active layer and a first gate; the first gate is located on a side of the first active layer away from the underlay substrate, and orthographic projections of the first gate and the first active layer on the underlay substrate are at least partially overlapped. The first active layer is electrically connected to the data line and the pixel electrode, respectively. The data line is located on a side of the first active layer close to the underlay substrate, and the pixel electrode is located on a side of the first gate away from the underlay substrate.

Abstract: A thin film transistor, a manufacturing method thereof, an array substrate and an electronic device arc provided. The thin film transistor includes an active layer including multiple oxide layers which includes a channel layer, a transition layer and a first barrier layer, the channel layer is an layer with a highest carrier mobility, the channel layer is a crystalline or amorphous oxide layer, the transition layer is in direct contact with the channel layer, the first barrier layer is an outermost oxide layer, the first barrier layer and the transition layer are both crystalline oxide layers; a crystallization degree of the first barrier layer and a crystallization degree of the transition layer are greater than a crystallization degree of the channel layer, and a band gap of the first barrier layer and a band gap of the transition layer are larger than a band gap of the channel layer.

Abstract: An array substrate includes a base substrate, a first conductive layer, a first electrode, an organic planarization layer and an organic active layer. The first conductive layer is provided on a side of the base substrate. The first electrode is provided on a side of the first conductive layer away from the base substrate, an orthographic projection of the first electrode on the base substrate overlapping an orthographic projection of the drain electrode on the base substrate. The organic planarization layer is provided on a side of the first electrode away from the base substrate, first via holes being provided in the organic planarization layer. The organic active layer is provided on a side of the organic planarization layer away from the base substrate, the organic active layer being connected to the source electrode by a first via hole and connected to the drain electrode by a first via hole.

Abstract: A thin film transistor includes a substrate; and a semiconductor layer a gate, a source electrode and a drain electrode; which are arranged on the substrate. The semiconductor layer includes a first material layer and a second material layer which are stacked, wherein a material of the first material layer is selected from one of or a combination of first n-type metal oxide semiconductor materials, and a material of the second material layer is selected from one of or a combination of second n-type metal oxide semiconductor materials. A carrier mobility of a first n-type metal oxide semiconductor material is greater than or equal to 40 cm2/Vs, and a second n-type metal oxide semiconductor material is doped with Y, Y being selected from one of or a combination of rare earth elements. The first material layer is closer to the gate than the second material layer.

Abstract: At least one embodiment of the present disclosure provides a display panel, and the display panel includes: a first substrate and a second substrate oppositely combined with each other, the first substrate includes a base substrate, and a gate line, a first electrode, a first interlayer insulating layer, and second electrode on the base substrate; the first interlayer insulating layer includes a first via hole penetrating through the first interlayer insulating layer, the second electrode is electrically connected to the first electrode the first via hole, first support structure is provided in a region corresponding to the first via hole and on a side of the second electrode away from the base substrate; at least a part of the first support structure is located in the first via hole, an orthographic projection of the first via hole overlaps with an orthographic projection of the gate line on the base substrate.

Abstract: The present disclosure relates to an OLED display panel and display device. The OLED display panel includes: a display area, a bending area and a bonding area, the display panel further includes: a base substrate; a first semiconductor pattern on the base substrate; a first insulating layer group on the first semiconductor pattern; a second semiconductor pattern on the first insulating layer group; a second insulating layer group on the second semiconductor pattern; first via holes in the first insulating layer group and the second insulating layer group; second via holes in the second insulating layer group, the display panel further includes: a metal trace, located on a side of the second insulating layer group away from the base substrate, and configured to connect a trace in the display area to a circuit board of the bending area; and a second source electrode and/or a second drain electrode.

Abstract: A thin film transistor, a manufacturing method thereof, a display substrate, and a display device are provided. The thin film transistor includes: a substrate, an active layer, a gate, a source and a drain. The active layer is arranged on the substrate and formed as a grid, including silicon nanowires extending along a first direction, the active layer includes source and drain regions oppositely arranged along the first direction, and a channel region located therebetween. The gate is arranged on the substrate, and an orthographic projection of the gate onto the substrate overlaps with orthographic projections for silicon nanowires in the channel region onto the substrate. The source and drain are arranged on the substrate, the source contacts silicon nanowires in the source region, and the drain contacts silicon nanowires in the drain region.

Abstract: An oxide thin film transistor, a preparation method thereof, and an electronic device are provided. The oxide thin film transistor includes a base substrate, a gate electrode and a metal oxide semiconductor layer, a gate insulation layer arranged between the metal oxide semiconductor layer and the gate electrode; the gate insulation layer includes a silicon oxide insulation layer and a silicon nitride layer, the silicon nitride layer adopts a single-layer structure or include a plurality of silicon nitride sublayers which are sequentially stacked, the silicon oxide insulation layer is between the silicon nitride layer and the metal oxide semiconductor layer; at least a part of a region in the silicon nitride layer satisfies that the percentage content of Si—H bonds in the sum of Si—N bonds, N—H bonds and Si—H bonds is not more than 7.

Abstract: The present disclosure relates to the field of display technologies, and in particular to a thin film transistor and a method for manufacturing the same, an array substrate and a display device. An active layer of the thin film transistor includes at least two metal oxide semi-conductor layers, the at least two metal oxide semi-conductor layers include a channel layer and a first protection layer, and metals in the channel layer include at least one of indium, gallium and zinc. Praseodymium is doped into the channel layer. And, in the channel layer, a number density of praseodymium atoms in the channel layer gradually decreases with a distance from the first protection layer.

Abstract: A circuit board includes a substrate, a first conductive layer, a first insulating layer and a second conductive layer. The first conductive layer includes a plurality of first conductive portions. The second conductive layer includes a plurality of second conductive portions. A second conductive portion passes through a first via hole in the first insulating layer to be in electrical contact with a first conductive portion. The first conductive layer and the second conductive layer each include at least one main conductive layer, which is capable of creating a first intermetallic compound with solder. At least one of the first conductive layer and the second conductive layer further includes a stop layer capable of creating a second intermetallic compound with the solder. A rate of a reaction between the stop layer and the solder is lower than a rate of a reaction between the main conductive layer and the solder.

Abstract: A thin film transistor, a shift register unit, a gate driving circuit and a display panel are provided. The M source branches and the N drain branches extend along a first direction and are arranged at intervals; in each of the P source-drain units, the M source branches and the N drain branches are alternately arranged, and M is greater than or equal to N; a semiconductor layer includes sub-channel regions between one drain branch and one source branch adjacent to each other; a sum of widths of the sub-channel regions of the P source-drain units in the first direction is W, and an average length of the sub-channel regions of the P source-drain units in a direction perpendicular to the first direction is L; 12?W/L?400, P, M and N are integers greater than or equal to 1, and P×N?4.