Patents by Inventor Ce Ning

Ce Ning has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230015871
    Abstract: A thin film transistor, a manufacturing method thereof, an array substrate and an electronic device arc provided. The thin film transistor includes an active layer including multiple oxide layers which includes a channel layer, a transition layer and a first barrier layer, the channel layer is an layer with a highest carrier mobility, the channel layer is a crystalline or amorphous oxide layer, the transition layer is in direct contact with the channel layer, the first barrier layer is an outermost oxide layer, the first barrier layer and the transition layer are both crystalline oxide layers; a crystallization degree of the first barrier layer and a crystallization degree of the transition layer are greater than a crystallization degree of the channel layer, and a band gap of the first barrier layer and a band gap of the transition layer are larger than a band gap of the channel layer.
    Type: Application
    Filed: May 27, 2021
    Publication date: January 19, 2023
    Applicant: BOE Technology Group Co., Ltd.
    Inventors: Jie Huang, Ce Ning, Zhengliang Li, Hehe Hu, Jiayu He, Nianqi Yao, Feng Qu, Xiaochun Xu
  • Publication number: 20230006070
    Abstract: A semiconductor substrate manufacturing method and a semiconductor substrate. The manufacturing method includes: forming a first semiconductor layer on the base substrate at a first temperature with a first oxide semiconductor material; forming the second semiconductor layer directly on the first semiconductor layer with a second oxide semiconductor material; and performing a patterning process such that the first semiconductor layer and the second semiconductor layer are respectively patterned into a seed layer and a first channel layer. Both the first oxide semiconductor material and the second oxide semiconductor material are capable of forming crystalline phases at a second temperature, the second temperature is less than or equal to 40° C., and the first temperature is greater than or equal to 100° C.
    Type: Application
    Filed: May 27, 2021
    Publication date: January 5, 2023
    Applicant: BOE Technology Group Co., Ltd.
    Inventors: Jie Huang, Ce Ning, Zhengliang Li, Hehe Hu, Jiayu He, Nianqi Yao, Kun Zhao, Feng Qu, Xiaochun Xu
  • Patent number: 11534755
    Abstract: The present disclosure relates to a micro-channel device. The micro-channel device may include a micro-channel structure and a semiconductor junction. The micro-channel structure may include a base layer, a plurality of rails distributed on the base layer at intervals, and a cover layer comprising a plurality of columns. The cover layer and the base layer are configured to form a plurality of micro-channels. The semiconductor junction may include a P-type semiconductor layer, an intrinsic semiconductor layer and a N-type semiconductor layer stacked in a first direction.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: December 27, 2022
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Ce Ning, Xiaochen Ma, Hehe Hu, Guangcai Yuan, Xin Gu
  • Patent number: 11532686
    Abstract: An array substrate includes a base substrate; a first thin film transistor on the base substrate and including a first active layer, a first gate electrode, a first source electrode and a first drain electrode; a second thin film transistor on the base substrate and including a second active layer, a second gate electrode, a second source electrode and a second drain electrode; a first gate insulating layer between the first active layer and the first gate electrode; and a second gate insulating layer between the second active layer and the second gate electrode, the second gate insulating layer being different from the first gate insulating layer. The first source electrode, the first drain electrode, and the second gate electrode are in a same layer. The first source electrode and the first drain electrode are on a side of the second gate insulating layer distal to the base substrate.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: December 20, 2022
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Xinhong Lu, Ke Wang, Hehe Hu, Ce Ning, Wei Yang
  • Publication number: 20220375966
    Abstract: An array substrate includes a base substrate, a driving circuit layer, and a functional device layer which are sequentially stacked; the driving circuit layer is provided with first driving circuits, and each first driving circuit at least comprises a driving transistor; and the driving circuit layer comprises a first gate layer, a first gate insulation layer, a semiconductor layer, a second gate insulation layer, a second gate layer, an interlayer dielectric layer, and a source-drain metal layer which are sequentially stacked on one side of the base substrate.
    Type: Application
    Filed: May 18, 2021
    Publication date: November 24, 2022
    Applicant: BOE Technology Group Co., Ltd.
    Inventors: Xue DONG, Guangcai YUAN, Ce NING, Zhiwei LIANG, Feng GUAN, Zhaohui QIANG, Yingwei LIU, Ke WANG, Zhanfeng CAO
  • Publication number: 20220352283
    Abstract: An organic electroluminescent display substrate is provided, which includes a base substrate, and a light-emitting unit and a light-sensing unit arranged on the base substrate, wherein the light-sensing unit is arranged on a light-emitting side of the light-emitting unit, and configured for sensing an intensity of light emitted from the light-emitting unit; a first planarization layer is arranged between the light-sensing unit and the light-emitting unit; the light-sensing unit comprises a first thin film transistor and a photosensitive sensor arranged sequentially in that order in a direction away from the base substrate, and a second planarization layer is arranged between the photosensitive sensor and the first thin film transistor. A display panel, a display device and a method for manufacturing the organic electroluminescent display substrate are further provided.
    Type: Application
    Filed: November 13, 2020
    Publication date: November 3, 2022
    Inventors: Jiayu HE, Ce NING, Zhengliang LI, Hehe HU, Jie HUANG, Nianqi YAO, Xue LIU
  • Publication number: 20220344517
    Abstract: A thin film transistor includes a gate electrode, an active layer, a gate insulating layer located between the gate electrode and the active layer, and a source electrode and a drain electrode electrically connected to the active layer. The active layer includes a channel layer and at least one channel protection layer; a material of each of the channel layer and the at least one channel protection layer is a metal oxide semiconductor material. The at least one channel protection layer is a crystallizing layer, and metal elements of the at least one channel protection layer include non-rare earth metal elements including In, Ga, Zn and Sn.
    Type: Application
    Filed: April 30, 2021
    Publication date: October 27, 2022
    Applicant: BOE Technology Group Co., Ltd.
    Inventors: Jie Huang, Zhengliang Li, Ce Ning, Hehe Hu, Nianqi Yao, Kun Zhao, Fengjuan Liu, Tianmin Zhou, Liping Lei
  • Publication number: 20220344480
    Abstract: The present disclosure provides a thin film transistor, a GOA circuit and an array substrate, the thin film transistor including a source electrode, including a source electrode wiring and a plurality of source electrode branches; a drain electrode, including a drain electrode wiring and a plurality of drain electrode branches; a gate; a semiconductor layer including a plurality of semiconductor branches; a plurality of source electrode branches. The plurality of drain electrode branches are in contact with the plurality of semiconductor branches and are divided into a plurality of cells; the source electrode wiring and the drain electrode wiring are arranged in a parallel and spaced apart, and the number m of one of the source electrode wiring and the drain electrode wiring is an integer greater than or equal to 2, and the number n of the other is an integer greater than or equal to 1.
    Type: Application
    Filed: May 19, 2021
    Publication date: October 27, 2022
    Applicant: BOE Technology Group Co., Ltd.
    Inventors: Lizhong Wang, Ce Ning, Hehe Hu, Tianmin Zhou, Jipeng Song
  • Patent number: 11446661
    Abstract: A microfluidic channel and a preparation method and an operation method thereof. The microfluidic channel includes: a channel structure, including a channel for a liquid sample to flow through and a channel wall surrounding the channel. The channel wall includes an electrolyte layer made of an electrolyte material; and a control electrode layer, at a side of the electrolyte layer away from the channel. The control electrode layer overlaps with the electrolyte layer with respect to the channel.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: September 20, 2022
    Assignee: Beijing BOE Technology Development Co., Ltd.
    Inventors: Xiaochen Ma, Guangcai Yuan, Ce Ning, Zhengliang Li
  • Publication number: 20220276540
    Abstract: The disclosure provides an array substrate, a manufacturing method thereof and a display panel, and relates to the technical field of display. The array substrate comprises a first transistor arranged on one side of a substrate base, the first transistor being located in an active area of the array substrate; a flat layer covering the first transistor, the flat layer having a first through-hole; a first electrode layer arranged in the first through-hole, and being connected with a drain of the first transistor and having a first groove; a filling layer arranged in the first groove; and a second electrode layer arranged on a side, away from the first transistor, of the filling layer, the second electrode layer being connected with the first electrode layer. So an electric field for driving a liquid crystal layer is more uniform, thereby improving an aperture ratio of the display panel.
    Type: Application
    Filed: October 18, 2021
    Publication date: September 1, 2022
    Inventors: Lizhong WANG, Ce NING, Binbin TONG, Zhen ZHANG, Fuqiang LI, Zhenyu ZHANG
  • Publication number: 20220278162
    Abstract: An array substrate includes a substrate, the array substrate includes a display region and a detection region. And the detection region includes a thin film transistor located on the substrate and a photodiode located on one side of the thin film transistor away from the substrate, and the array substrate further includes a first inorganic protective layer, an organic protective layer and a second inorganic protective layer located between the thin film transistor and the photodiode. And the first inorganic protective layer, the organic protective layer and the second inorganic protective layer are stacked in sequence in a direction away from the substrate, and an orthographic projection of the photodiode on the substrate is within the range of the orthographic projection of the organic protective layer on the substrate.
    Type: Application
    Filed: August 24, 2021
    Publication date: September 1, 2022
    Inventors: Jiayu HE, Ce NING, Zhengliang LI, Hehe HU, Jie HUANG, Nianqi YAO, Kun ZHAO
  • Publication number: 20220255025
    Abstract: The present disclosure relates to an OLED display panel and display device. The OLED display panel includes: a display area, a bending area and a bonding area for bonding a circuit board, wherein the display panel further includes: a base substrate; a first semiconductor pattern on the base substrate; a first insulating layer group on the first semiconductor pattern; a second semiconductor pattern on the first insulating layer group; a second insulating layer group on the second semiconductor pattern; first via holes in the first insulating layer group and the second insulating layer group; second via holes in the second insulating layer group, wherein the display panel further includes: a first groove located in the bending area and having a depth substantially identical to that of the first via holes; and a metal trace, connecting a trace in the display area to the circuit board.
    Type: Application
    Filed: April 29, 2022
    Publication date: August 11, 2022
    Inventors: Wei YANG, Guangcai YUAN, Ce NING, Xinhong LU, Tianmin ZHOU, Xin YANG
  • Publication number: 20220223745
    Abstract: A thin film transistor, a manufacturing method thereof, a display substrate, and a display device are provided. The thin film transistor includes: a substrate, an active layer, a gate, a source and a drain. The active layer is arranged on the substrate and formed as a grid, including silicon nanowires extending along a first direction, the active layer includes source and drain regions oppositely arranged along the first direction, and a channel region located therebetween. The gate is arranged on the substrate, and an orthographic projection of the gate onto the substrate overlaps with orthographic projections for silicon nanowires in the channel region onto the substrate. The source and drain are arranged on the substrate, the source contacts silicon nanowires in the source region, and the drain contacts silicon nanowires in the drain region.
    Type: Application
    Filed: May 18, 2021
    Publication date: July 14, 2022
    Inventors: Jiayu HE, Ce NING, Zhengliang LI, Hehe HU, Jie HUANG, Nianqi YAO, Zhi WANG, Feng GUAN
  • Publication number: 20220208070
    Abstract: A shift register unit includes an input sub-circuit, a pull-down node driving sub-circuit and an output sub-circuit. The pull-down node driving sub-circuit includes a first connection unit, a first voltage-reduction unit and a second connection unit, and configured to: under the control of the first voltage signal terminal and the pull-up node, transmit a first voltage signal from the first voltage signal terminal to the first pull-down node via the first connection unit, and reduce a voltage applied to the second connection unit via the first voltage-reduction unit; and transmit a second voltage signal from the second voltage signal terminal to the first pull-down node via the second connection unit under the control of the pull-up node.
    Type: Application
    Filed: November 24, 2021
    Publication date: June 30, 2022
    Inventors: Shuilang DONG, Shanshan XU, Guangcai YUAN, Zhanfeng CAO, Ce NING, Lizhong WANG, Dapeng XUE, Nianqi YAO
  • Publication number: 20220186359
    Abstract: A fixture, a tray and a sputtering system. The fixture is internally provided with a support structure and a clamping structure connected with each other, wherein the clamping structure is configured to clamp a to-be-sputtered substrate; an orthographic projection of the clamping structure on a plane where the support structure is located and the support structure share an superimposed area and are separate in non-superimposed areas; wherein the support structure located in the non-superimposed area and/or the clamping structure located in the non-superimposed area has a first hollowed structure. The fixture is internally provided with the first hollowed structure, such that a part of an area of the to-be-sputtered substrate covered by the fixture may be exposed via the first hollowed structure when the fixture holds the to-be-sputtered substrate, so as to reduce the area of the to-be-sputtered substrate covered by the fixture.
    Type: Application
    Filed: September 24, 2021
    Publication date: June 16, 2022
    Inventors: Nianqi YAO, Ce NING, Zhengliang LI, Hehe HU, Dapeng XUE, Lizhong WANG, Shuilang DONG, Jie HUANG, Jiayu HE, Lubin SHI, Yancai LI
  • Patent number: 11362114
    Abstract: A method of manufacturing an array substrate includes: forming a first semiconductor pattern and a first insulating layer group sequentially on a base substrate; forming a second semiconductor pattern and a second insulating layer group sequentially on the first insulating layer group; forming two first via holes in the first insulating layer group and the second insulating layer group to expose the first semiconductor pattern, annealing the exposed first semiconductor pattern and then removing an oxide layer on a surface of the first semiconductor pattern; forming connecting wires in the first via holes; forming second via holes in the second insulating layer group to expose the second semiconductor pattern, and forming a first source electrode and a first drain electrode in the second via holes such that the first source electrode or the first drain electrode covers and is connected to one of the connecting wires.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: June 14, 2022
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Wei Yang, Guangcai Yuan, Ce Ning, Xinhong Lu, Tianmin Zhou, Xin Yang
  • Publication number: 20220126294
    Abstract: A biochip and a method for manufacturing the same are provided. The biochip includes: a guide layer; a channel layer on the guide layer, wherein the channel layer has therein a plurality of first channels extending in a first direction; a plurality of second channels extending in a second direction, wherein each of the plurality of second channels is in communication with the plurality of first channels, the plurality of second channels are in a layer where the channel layer is located, or in a layer where the channel layer and the guide layer are located; an encapsulation cover plate on a side of the channel layer distal to the guide layer; and a driving unit configured to drive biomolecules to move.
    Type: Application
    Filed: January 22, 2021
    Publication date: April 28, 2022
    Inventors: Xiaochen MA, Ce NING, Guangcai YUAN, Xin GU, Zhengliang LI
  • Patent number: 11257849
    Abstract: A display panel and a method for fabricating the same are provided. The display panel includes: a base substrate; a first thin film transistor on one side of the base substrate, the first thin film transistor comprising: a first active layer, a first protection layer, a second protection layer, a first source and a first drain; wherein the first protection layer and the second protection layer are on one side of the first active layer away from the base substrate, and are separated from each other; the first protection layer and the second protection layer are configured to protect the first active layer from being etched during forming of a via-hole corresponding to the first source and/or a via-hole corresponding to the first drain.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: February 22, 2022
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Wei Yang, Guangcai Yuan, Ce Ning, Xinhong Lu
  • Patent number: 11257954
    Abstract: Provided are a thin film transistor including: a base cushion layer having a recessed portion, base insulating layer, source-drain layer and active layer. The base insulating layer is located on a side of the base cushion layer where the recessed portion is located, and has a first and second partition walls that are spaced apart, and an orthographic projection region of a gap region between the first and second partition walls onto the base cushion layer is located at a region where the recessed portion is located; and both orthographic projection regions of the first and second partition walls onto the base cushion layer partially overlap with the recessed portion region; and both the source-drain layer and the active layer are located on the side of the base insulating layer away from the base cushion layer.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: February 22, 2022
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xiaochen Ma, Guangcai Yuan, Ce Ning, Xin Gu, Hehe Hu
  • Publication number: 20220048028
    Abstract: A microfluidic channel backplane includes a base, and a plurality of microfluidic channels, a sample-adding channel and an enrichment channel that are disposed above the base. Each microfluidic channel of the plurality of microfluidic channels includes a first end and a second end. The sample-adding channel is communicated with first ends of the plurality of microfluidic channels. The enrichment channel includes a first enrichment sub-channel and a second enrichment sub-channel. The first enrichment sub-channel is communicated with second ends of the plurality of microfluidic channels, and one end of the second enrichment sub-channel is communicated with the first enrichment sub-channel.
    Type: Application
    Filed: January 23, 2020
    Publication date: February 17, 2022
    Inventors: Xiaochen MA, Ce NING, Chao LI, Jiayu HE, Xueyuan ZHOU, Xiao ZHANG, Xin GU, Zhengliang LI, Guangcai YUAN