Abstract: Voltage providing unit, voltage providing method, display driving module and display device are provided. The voltage providing unit, applied to a display panel, is configured to provide a control voltage signal for a driving circuit, and the voltage providing unit includes a buck circuit and a first electrical level converting circuit. The buck circuit is configured to receive a first voltage signal and perform a buck operation on the first voltage signal to obtain a second voltage signal; and the first electrical level converting circuit is connected to the buck circuit, and is configured to receive an input control voltage, a third voltage signal and the second voltage signal, and to generate the control voltage signal in accordance with the input control voltage, the third voltage signal and the second voltage signal, a voltage value of the control voltage signal is less than a predetermined voltage value.

Abstract: The present disclosure provides a TFT, a manufacturing method and a display substrate, and it relates to the field of TFT technology. The TFT includes: a base substrate; a gate electrode arranged on the base substrate; an active layer arranged at a side of the gate electrode away from the base substrate, an orthogonal projection of the active layer onto the base substrate overlapping with an orthogonal projection of the gate electrode onto the base substrate; and a source electrode and a drain electrode arranged at a side of the active layer away from the base substrate and coupled to the active layer. A resistance between the gate electrode and the drain electrode is greater than a resistance between the gate electrode and the source electrode. According to the present disclosure, it is able to increase a withstand voltage range of the TFT.

Abstract: The present disclosure provides an array substrate, a display panel, and a method for manufacturing the array substrate, belonging to the field of display technologies. In the array substrate, a first electrode having a higher voltage in the first electrode and a second electrode of the transistor is disposed between an active layer and a base in a lower lap manner, and the second electrode having a lower voltage is disposed on a first insulating layer in an upper lap manner or disposed below the first insulating layer in the lower lap manner. When the second electrode is disposed in the upper lap manner, the problem that the transistor cannot operate normally due to the too large resistance at the second electrode can be avoided.

Abstract: Provided is an array substrate. The array substrate includes: a substrate, multiple data lines disposed on a side of the substrate, multiple active patterns disposed on a side, distal to the substrate, of the multiple data lines, wherein the multiple active patterns correspond to the multiple data lines, and each active pattern includes a first conductive section and two second conductive sections disposed on two sides of the first conductive section, respectively, and the first conductive section of the active pattern is electrically connected to a data line corresponding to the first conductive section; and multiple pixel electrodes disposed on a side, distal to the substrate, of the multiple active patterns, wherein the two second conductive sections in the active pattern are electrically connected to two different pixel electrodes, respectively.

Abstract: Provided is a micro-nano fluidic substrate, a chip, a preparation method, and a system. The micro-nano fluidic substrate includes: a base; an electrode layer located on the base, the electrode layer includes a first electrode, a second electrode, and a control electrode; and a film layer located on the electrode layer and far away from the base, the film layer includes a groove layer, a nano-channel and a micro-channel, the groove layer includes a first groove, the nano-channel is located in the first groove, an orthographic projection of the nano-channel on the base at least partially coincides with an orthographic projection of the control electrode on the base, and the micro-channel is in communication with the nano-channel, the micro-channel includes a first micro-channel and a second micro-channel, and the first micro-channel is in communication with the first electrode, the second micro-channel is in communication with the second electrode.

Abstract: A display substrate and a display device are provided. The display substrate includes: a base substrate, and a low temperature poly-silicon thin film transistor and a metal oxide thin film transistor on the base substrate; the low temperature poly-silicon thin film transistor includes: a low temperature poly-silicon semiconductor layer, a first gate insulating layer, a first gate electrode, a first interlayer insulating layer, a first source electrode, and a first drain electrode; the metal oxide thin film transistor includes: a metal oxide semiconductor layer, a second gate insulating layer, a second gate electrode, a second interlayer insulating layer, a passivation layer, a second source electrode, and a second drain electrode; and the second drain electrode is on a side of the metal oxide semiconductor layer away from the base substrate.

Abstract: A driving backplane includes a first substrate, a thick copper layer, a second substrate, and a driving layer stacked in sequence. The thick copper layer is provided with a driving wire configured to load a driving signal. The driving layer is provided with a driving circuit. The driving circuit is electrically connected to the driving wire through a via.

Abstract: A thin-film transistor and an array substrate are provided. The thin-film transistor includes a substrate and an active layer on the substrate. The active layer includes multiple layers of oxides arranged in a stacked manner; the multiple layers of oxides include a channel layer, a transition layer, and a first barrier layer; the channel layer is a layer having the maximum carrier mobility in the multiple layers of oxides; the channel layer is a crystalline oxide layer or an amorphous oxide layer; the transition layer is in direct contact with the channel layer; the first barrier layer is the outermost oxide layer among the multiple layers of oxide; the first barrier layer and the transition layer are both crystalline oxide layers; the band gap of the first barrier layer and the band gap of the transition layer are both greater than the band gap of the channel layer.

Abstract: A functional backplane includes a wiring board, an intermetallic compound layer and a conductive connection layer. The wiring board includes a substrate, conductive pads and a plurality of protective layer groups. The conductive pads are disposed on the substrate and configured to transmit a driving signal. The plurality of protective layer groups are stacked on a side of the conductive pads away from the substrate. A protective layer group in the plurality of protective layer groups includes an oxidation protective layer, where a material of the oxidation protective layer includes a nickel-based alloy. In a direction perpendicular to the substrate and directed from the substrate to the protective layer group, the oxidation protective layer, the intermetallic compound layer and the conductive connection layer are stacked in sequence.

Abstract: A method for manufacturing a thin film transistor, and a thin film transistor are provided. The method includes: forming an active layer on a substrate by a single patterning process; forming a gate insulating layer by deposition on a side of the active layer away from the substrate; forming a first via hole and a second via hole penetrating through the gate insulating layer by a single patterning process, the first and second via holes being located at two ends of the active layer respectively; and forming a first electrode, a gate electrode, and a second electrode on the gate insulating layer by a single patterning process, the first and second electrodes being connected to the active layer through the first and second via holes, respectively, and an orthographic projection of the gate electrode on the substrate at least partially overlapping that of the active layer on the substrate.

Abstract: A wiring board includes a base substrate and first connection pads disposed on the base substrate. The first connection pads each include electrical connection layer(s); each electrical connection layer includes a main material layer and protective layer(s) disposed on a side of the main material layer away from the base substrate; the protective layer(s) include a first reference protective layer, which is a protective layer farthest away from the base substrate in the protective layer(s); and a material of the main material layer includes copper. The electrical connection layer(s) include a first electrical connection layer, which is an electrical connection layer farthest away from the base substrate in the electrical connection layer(s); and in protective layer(s) in the first electrical connection layer, at least a material of the first reference protective layer is capable of forming a first intermetallic compound with a first solder.

Abstract: A display substrate includes a base substrate and at least one transistor disposed on the base substrate, with a transistor including an active layer pattern disposed on the base substrate; a first source-drain electrode disposed on the base substrate and electrically connected with the active layer pattern; a first gate electrode disposed on a side of the active layer pattern away from the base substrate, the first gate electrode and the active layer pattern having overlapped orthographic projections on the base substrate and are not in contact with each other; a second source-drain electrode disposed on a side of the active lay pattern away from the base substrate and including a first sub-electrode and a second sub-electrode connected with each other, the second sub-electrode is located on a side of the first sub-electrode close to the first gate electrode, the first sub-electrode is electrically connected with the active layer pattern.

Abstract: A display substrate and a display panel are provided, the display substrate includes a first gate driver circuit and a second gate driver circuit that are respectively arranged on a first side and a second side of a display region opposite to each other; the first gate driver circuit includes a plurality of first shift register units arranged in a first direction, each first shift register unit includes a first thin film transistor; the second gate driver circuit includes a plurality of second shift register units arranged in the first direction, each second shift register unit includes a second thin film transistor having the same function as the first thin film transistor; a display region includes a sub-pixel including a third thin film transistor, the third thin film transistor includes a third active layer, the third active layer comprises a plurality of metal oxide semiconductor layers.

Abstract: A display panel includes base substrate, second conductive layer, second active layer, third gate insulating layer, third conductive layer in sequence. The second conductive layer includes first conductive part forming first gate of first transistor. The second active layer includes first active part including first and second sub-active parts and third sub-active part therebetween. The first and second sub-active parts form first and second electrodes of first transistor, and portion of the third sub-active part forms channel region of first transistor. Orthographic projection of the first conductive part on the base substrate covers that of the third sub-active part. Orthographic projection of the third gate insulating layer on the base substrate covers that of the first active part. The third conductive layer includes second conductive part forming second gate of first transistor. Orthographic projection of the second conductive part on the base substrate covers that of the channel region.

Abstract: Provided is an array substrate. The array substrate includes a base; a light-reflective pattern disposed on the base, a plurality of first gate signal lines disposed on a side of the light-reflective pattern away from the base; and a plurality of data signal lines disposed on a side of the plurality of first gate signal lines away from the base. The light-reflective pattern includes a plurality of reflective portions, and an opening region is defined between two adjacent reflective portions of the plurality of reflective portions. An orthographic projection of the first gate signal line on the base and an orthographic projection of the data signal line on the base have a first overlapping region, and at least one first overlapping region of a plurality of first overlapping regions is within an orthographic projection of the reflective portion on the base.

Abstract: A thin film transistor including a base substrate, and a drain, a source and an active layer on the base substrate, where the drain and the source are in different layers, respectively, and any two of an orthographic projection of the drain on the base substrate, an orthographic projection of the source on the base substrate and an orthographic projection of the active layer on the base substrate at least partially overlap each other.

Abstract: A circuit board and a display device are disclosed. The circuit board includes: a base substrate including a device area; a plurality of first pads located on a side of the base substrate and in the device area, where a material of the first pads includes Cu; an oxidation protection layer located on a side away from the base substrate, of the first pads, where the plurality of first pads are bonded to a plurality of electronic components through the oxidation protection layer; a material of the oxidation protection layer includes CuaMgbXc, where X includes one or any combination of Al, Sn, Pb, Au, Ag, In, Zn, Bi, Ga, V, W, Y, Zr, Mo, Nb, Pt, Co or Sb.

Abstract: A display substrate and a display panel are provided, the display substrate includes a first gate driver circuit and a second gate driver circuit that are respectively arranged on a first side and a second side of a display region opposite to each other; the first gate driver circuit includes a plurality of first shift register units arranged in a first direction, each first shift register unit includes a first thin film transistor including a first active layer, the first active layer includes a metal oxide semiconductor material; the second gate driver circuit includes a plurality of second shift register units arranged in the first direction, each second shift register unit includes a second thin film transistor having the same function as the first thin film transistor, and the second thin film transistor includes a second active layer, the second active layer includes a metal oxide semiconductor material.

Abstract: A driving circuit and a display device are provided. The driving circuit includes a pull-up node noise reduction circuit, an input circuit, a first output noise reduction circuit and a pull-down node noise reduction circuit; at least one transistor included in the driving circuit is a floating processing transistor including a floating electrode, a gate electrode, a first electrode and a second electrode; the floating electrode is arranged on the same layer with at least one of the first electrodes and the second electrode of the floating processing transistor; the floating electrode is arranged between the first electrode and the second electrode of the floating processing transistor, and the floating electrode has no electric signal input; a shortest distance between the first electrode of the floating processing transistor and the second electrode of the floating processing transistor is greater than an initial distance.

Abstract: A circuit board includes a substrate and a stress neutral layer disposed on a side of the substrate. The stress neutral layer includes one or more first metal layers and one or more second metal layers. The one or more second metal layers and the one or more first metal layers are stacked. At least one of the one or more first metal layers is made of a material for generating a tensile stress, and at least one of the one or more second metal layers is made of a material for generating a compressive stress.