Abstract: A microfluidic channel backplane includes a base, and a plurality of microfluidic channels, a sample-adding channel and an enrichment channel that are disposed above the base. Each microfluidic channel of the plurality of microfluidic channels includes a first end and a second end. The sample-adding channel is communicated with first ends of the plurality of microfluidic channels. The enrichment channel includes a first enrichment sub-channel and a second enrichment sub-channel. The first enrichment sub-channel is communicated with second ends of the plurality of microfluidic channels, and one end of the second enrichment sub-channel is communicated with the first enrichment sub-channel.

Abstract: Provided is a substrate. The substrate includes a base substrate; and a plurality of sub-pixel structures arranged in an array on the base substrate, wherein the sub-pixel structure comprises: a thin film transistor disposed on the base substrate, the thin film transistor comprising a source and a drain; an insulating layer disposed on a side of the thin film transistor distal from the base substrate, a first via hole being formed in the insulating layer; a pixel electrode disposed on a side of the insulating layer distal from the base substrate, the pixel electrode being electrically connected to either the source or the drain through the first via hole; and a filling block disposed at the first via hole.

Abstract: A displaying base plate and a manufacturing method thereof, and a displaying device. The displaying base plate includes a substrate, and a first electrode layer disposed on one side of the substrate, wherein the first electrode layer includes a first electrode pattern; a first planarization layer disposed on one side of the first electrode layer that is away from the substrate, wherein the first planarization layer is provided with a through hole, and the through hole penetrates the first planarization layer, to expose the first electrode pattern; and a second electrode layer, a second planarization layer and a third electrode layer that are disposed in stack on one side of the first planarization layer that is away from the substrate, wherein the second electrode layer is disposed closer to the substrate, the second electrode layer is connected to the first electrode pattern and the third electrode layer.

Abstract: A display substrate, a display panel and a display apparatus. The display substrate includes a first base substrate; a plurality of gate lines and a plurality of data lines which are arranged on a side of the first base substrate; the plurality of gate lines and the plurality of data lines are arranged to be intersected with each other and insulated from each other; a planarization layer, arranged on a side of the gate lines and the data lines away from the first base substrate, and including a first via hole; and a supporting structure, arranged on a side of the planarization layer away from the first base substrate and filled into the first via hole; and in a direction perpendicular to the first base substrate, a height of the supporting structure is greater than a depth of the first via hole.

Abstract: The present disclosure provides a shift register unit, a gate driving circuit and a display device. The shift register unit provided by the present disclosure includes: an input sub-circuit, an output sub-circuit, at least one pull-down control sub-circuit, at least one pull-down sub-circuit, at least one first noise reduction sub-circuit, and a reverse bias sub-circuit; the reverse bias sub-circuit is configured to control transistors in at least part of sub-circuits connected to a pull-up node to be in a reverse bias state through a power voltage signal in response to a potential of the pull-up node, or control the transistors in at least part of the sub-circuits connected to the pull-up node to be in the reverse bias state through a cascade signal in response to a potential of a cascade signal terminal.

Abstract: A biochip and a method for manufacturing the same are provided. The biochip includes: a guide layer; a channel layer on the guide layer, wherein the channel layer has therein a plurality of first channels extending in a first direction; a plurality of second channels extending in a second direction, wherein each of the plurality of second channels is in communication with the plurality of first channels, the plurality of second channels are in a layer where the channel layer is located, or in a layer where the channel layer and the guide layer are located; an encapsulation cover plate on a side of the channel layer distal to the guide layer; and a driving unit configured to drive biomolecules to move.

Abstract: The present disclosure provides a thin film transistor, a GOA circuit and an array substrate, the thin film transistor including a source electrode, including a source electrode wiring and a plurality of source electrode branches; a drain electrode, including a drain electrode wiring and a plurality of drain electrode branches; a gate; a semiconductor layer including a plurality of semiconductor branches; a plurality of source electrode branches. The plurality of drain electrode branches are in contact with the plurality of semiconductor branches and are divided into a plurality of cells; the source electrode wiring and the drain electrode wiring are arranged in a parallel and spaced apart, and the number m of one of the source electrode wiring and the drain electrode wiring is an integer greater than or equal to 2, and the number n of the other is an integer greater than or equal to 1.

Abstract: The disclosure provides a liquid crystal display panel and a display apparatus. The liquid crystal display panel of the disclosure includes: first and second substrates assembled to form a cell, a plurality of main spacers therebetween, and an auxiliary spacer around at least a portion of the main spacers. Height of the auxiliary spacer is greater than or equal to that of the main spacer. The display panel further includes: pillows on side of the first substrate close to the second substrate and each abutting against a corresponding main spacer. An orthographic projection of the main spacer on the first substrate falls within an orthographic projection of the pillow on the first substrate, and an orthographic projection of the auxiliary spacer on the first substrate does not overlap with the orthographic projection of the pillow on the first substrate.

Abstract: A display substrate, a manufacturing method thereof and a display apparatus are provided. In the present disclosure, a first transistor group with oxide semiconductor as an active layer material is disposed on a side of a second transistor group with polysilicon as an active layer material away from the base, and an area enclosed by orthographic projections of the transistors in the first transistor group on the base is overlapped with an area enclosed by orthographic projections of the transistors in the second transistor group on the base. Stable performance of the transistors included can be ensured in a manufacturing process of the first transistor group and the second transistor group located in different layers, and at the same time, an area occupied by the driving circuit can be reduced so as to decrease a frame width of a display apparatus or improve resolution of the display apparatus.

Abstract: The present disclosure provides a display substrate, a method for manufacturing the display substrate and a display panel. The display substrate includes: a first semiconductor layer on a base substrate, where an active layer of the first thin film transistor is in the first semiconductor layer, and the active layer of the first thin film transistor at least comprises a channel region and a drain contact region; an interlayer insulation layer on a side of the first semiconductor layer away from the base substrate; and a first conductive layer on a side of the interlayer insulation layer away from the first semiconductor layer, wherein the pixel electrode is located in the first conductive layer, and the pixel electrode in the pixel unit is directly and electrically connected to the drain contact region of the active layer of the first thin film transistor through a through hole.

Abstract: The present disclosure relates to an OLED display panel and display device. The OLED display panel includes: a display area, a bending area and a bonding area for bonding a circuit board, wherein the display panel further includes: a base substrate; a first semiconductor pattern on the base substrate; a first insulating layer group on the first semiconductor pattern; a second semiconductor pattern on the first insulating layer group; a second insulating layer group on the second semiconductor pattern; first via holes in the first insulating layer group and the second insulating layer group; second via holes in the second insulating layer group, wherein the display panel further includes: a first groove located in the bending area and having a depth substantially identical to that of the first via holes; and a metal trace, connecting a trace in the display area to the circuit board.

Abstract: A display substrate, including: a base substrate; and a metal conductive layer, located at a side of the base substrate, and including a core conductive layer and a functional conductive layer laminated along a direction away from the base substrate; a material of the core conductive layer includes a conductive metal material; a material of the functional conductive layer includes a first diffusion barrier metal material and a first adhesion force enhancing metal material, wherein the first diffusion barrier metal material is configured to block diffusion of the conductive metal material, and the first adhesion force enhancing metal material is configured to enhance an adhesion force between the functional conductive layer and a photoresist used in a patterning process of the functional conductive layer; a surface energy of any of first adhesion force enhancing metal materials is less than or equal to 325 mJ/m2.

Abstract: Provided is an array substrate. The array substrate includes a display region and a non-display region located at a periphery of the display region, wherein the array substrate includes a substrate; a first transistor and a second transistor that are disposed on the substrate, wherein the first transistor is disposed in the display region, and the second transistor is disposed in the non-display region; and a data line and a pixel electrode that are disposed in the display region, wherein the data line is disposed on a side of the first active layer close to the substrate and is lapped with the first active layer, and the pixel electrode is disposed on a side of the first gate facing away from the substrate and is lapped with the first active layer.

Abstract: Provided is a shift register unit. The shift register unit includes an input circuit, a compensation control circuit, and an output circuit; wherein input circuit coupled to an input signal terminal, an input control terminal, a first power supply terminal, a reference node, and a first node; the compensation control circuit coupled to a first clock signal terminal, the reference node, and the first node; and the output circuit coupled to the first node, a second clock signal terminal, and an output terminal.

Abstract: The present disclosure relates to the field of display technologies, and in particular to a thin film transistor and a method for manufacturing the same, an array substrate and a display device. An active layer of the thin film transistor includes at least two metal oxide semi-conductor layers, the at least two metal oxide semi-conductor layers include a channel layer and a first protection layer, and metals in the channel layer include tin, and at least one of indium, gallium and zinc. The first protection layer includes praseodymium used to absorb photo-generated electrons from at least one of the channel layer and the first protection layer which is under light irradiation and reduce a photo-generated current caused by the light irradiation.

Abstract: A display substrate and a display panel are provided, the display substrate includes a first gate driver circuit and a second gate driver circuit that are respectively arranged on a first side and a second side of a display region opposite to each other; the first gate driver circuit includes a plurality of first shift register units arranged in a first direction, each first shift register unit includes a first thin film transistor including a first active layer, the first active layer includes a metal oxide semiconductor material; the second gate driver circuit includes a plurality of second shift register units arranged in the first direction, each second shift register unit includes a second thin film transistor having the same function as the first thin film transistor, and the second thin film transistor includes a second active layer, the second active layer includes a metal oxide semiconductor material.

Abstract: A display panel includes base substrate, second conductive layer, second active layer, third gate insulating layer, third conductive layer in sequence. The second conductive layer includes first conductive part forming first gate of first transistor. The second active layer includes first active part including first and second sub-active parts and third sub-active part therebetween. The first and second sub-active parts form first and second electrodes of first transistor, and portion of the third sub-active part forms channel region of first transistor. Orthographic projection of the first conductive part on the base substrate covers that of the third sub-active part. Orthographic projection of the third gate insulating layer on the base substrate covers that of the first active part. The third conductive layer includes second conductive part forming second gate of first transistor. Orthographic projection of the second conductive part on the base substrate covers that of the channel region.

Abstract: A light-emitting substrate and a display device are disclosed, the light-emitting substrate includes: a base substrate including a light-emitting region; a plurality of first pads on a side of the base substrate and in the light-emitting region, where a material of the first pads includes Cu; and an oxidation protection layer on a side of the first pads away from the base substrate, where the plurality of first pads is used for bonding connection with a plurality of light-emitting units through the oxidation protection layer, a material of the oxidation protection layer includes CuNiX, and X includes one or any combination of Al, Sn, Pb, Au, Ag, In, Zn, Bi, Mg, Ga, V, W, Y, Zr, Mo, Nb, Pt, Co or Sb.

Abstract: A thin film transistor includes a first active layer, a second active layer, a first electrode, a second electrode and a third electrode. The first active layer includes a first surface away from a substrate. The second active layer includes a second surface in contact with the first surface. The first electrode, the first active layer and the second active layer have an overlapping region. The second electrode, the first active layer and the second active layer have an overlapping region. The third electrode, the first active layer and the second active layer have an overlapping region, and the third electrode is opposite to the second electrode. The second surface is located within the first surface, and a distance between at least part of a border of the second surface and a border of the first surface is less than or equal to 0.5 ?m.

Abstract: A liquid crystal display device, a method for displaying an image, and an electronic device are provided. In the first operation mode, a control circuit of the display device is configured to: receive display data of an mth image frame, and control the display device to display n sub-field images. The display data includes initial gray scales under n base colors. In a sub-field image of the mth image frame: pixels include a target pixel, and an actual gray scale of the target pixel is an average of an intermediate gray scale and initial gray scales of T non-target pixels. An actual gray scale of at least a part of non-target pixels is an initial gray scale thereof. The target pixel meets at least one of a first condition and a second condition.