Abstract: Provided are a display substrate, display panel and display apparatus. The display substrate includes: a base substrate; a plurality of sub-pixels on a side of the base substrate, where each of the plurality of sub-pixels includes a sub-pixel opening region; an inorganic color-resist layer, on the same side as the plurality of sub-pixels, including a plurality of color-resist units, where an orthographic projection of the color-resist unit on the base substrate covers an orthographic projection of the sub-pixel opening region, and a light emitting color of the color-resist unit is same as a color of its corresponding sub-pixel; the color-resist unit includes at least two inorganic sub-layers stacked alternately, and different inorganic sub-layers have different refractive indexes.

Abstract: A display substrate and a display device. The display substrate includes a base substrate, and at least three functional layers, at least two first adaptation layers and a target connection member arranged on the base substrate. At least two functional layers of the at least three functional layers are laminated one on another in a direction away from the base substrate, and the at least three functional layers include a target functional layer. The at least two first adaptation layers include a top adaptation layer and at least one bottom adaptation layer, the top adaptation layer is arranged at a side of the target functional layer away from the base substrate, and at least a part of the bottom adaptation layer is arranged between the target functional layer and the base substrate.

Abstract: The present disclosure discloses an array substrate and a display device. The array substrate includes a base substrate (13) and a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer which are sequentially stacked on a side of the base substrate (13). The fourth conductive layer includes a common electrode (21), a material of the fourth conductive layer is a transparent conductive oxide material, a material of the third conductive layer is a metal conductive material, and at least a portion of a surface of the third conductive layer away from the base substrate (13) is in contact with at least a portion of a surface of the fourth conductive layer close to the base substrate (13).

Abstract: A thin film transistor includes a first electrode, a second electrode, an active layer, and a gate electrode disposed on a base substrate. The first electrode is located on a side of the active layer close to the base substrate, and a first insulation layer is disposed between the first electrode and the active layer, and is provided with a first via. The active layer is electrically connected to the first electrode through the first via. A second insulation layer is disposed between the gate electrode and the active layer. An orthographic projection of the gate electrode is overlapped, at least partially, with an orthographic projection of the first via, on the base substrate, a surface of a side of the gate electrode close to the base substrate is a first surface, a surface of a side of the gate electrode away from the base substrate is a second surface.

Abstract: The present disclosure provides a metal oxide thin film transistor, a semiconductor device and a display device, belongs to the field of display technology, and can solve a problem that current metal oxide thin film transistors have a poor stability. The metal oxide thin film transistor of the present disclosure includes a substrate and a first metal oxide semiconductor layer on the substrate; a material of the first metal oxide semiconductor layer includes a metal oxide doped with a first metal element, an electronegativity difference value between the first metal element and an oxygen element is greater than or equal to an electronegativity difference value between a metal element in the metal oxide and the oxygen element.

Abstract: An array substrate and a display device are provided. The array substrate includes a base substrate (12), and at least one transistor (11), at least one data line (DL) and at least one first electrode (10) disposed on the base substrate (12). The at least one transistor (11) includes an active layer (17), the active layer (17) includes two or more sub-active layers arranged in a stack, the two or more sub-active layers includes a first sub-active layer, the first sub-active layer is closer to the base substrate (12) than other sub-active layers. The first sub-active layer includes a first channel region (170-1) and a first sub-region (171-1) and a third sub-region (172-3) located on two opposite sides of the first channel region (170-1). The data line (DL) is electrically connected with the first sub-region (171-1), and the first electrode (10) is electrically connected with the third sub-region (172-3).

Abstract: There is provided a metal oxide thin film transistor, including: a substrate and a metal oxide semiconductor layer on the substrate; a gate and a gate insulating layer between the substrate and the metal oxide semiconductor layer; the gate insulating layer includes a first silicon nitride layer, a second silicon nitride layer and a first silicon oxide layer which are stacked; the first silicon oxide layer is in contact with the metal oxide semiconductor layer, and two surfaces of the second silicon nitride layer are in contact with the first silicon nitride layer and the first silicon oxide layer, respectively; a content of hydrogen atoms of at least a partial region of the second silicon nitride layer is less than 30% of a content of hydrogen atoms of at least a partial region of the first silicon nitride layer. An array substrate and a display device are further provided.

Abstract: A wiring board include a base substrate, an active pattern layer, and an electrical pattern layer. The active pattern layer is arranged on a side of the base substrate and includes a plurality of active patterns. The electrical pattern layer is arranged on a side of the active pattern layer away from the base substrate, and includes a plurality of connection portions, and at least one connection portion is coupled to an active pattern. A connection portion includes a plurality of first sub-layers which are stacked arranged in a thickness direction of the base substrate, two first sub-layers are farthest away from the base substrate among the plurality of first sub-layers are a first conductive sub-layer and a first protective sub-layer. The first protective sub-layer is arranged on a side of the first conductive sub-layer away from the base substrate, and the material of the first protective sub-layer includes nickel.

Abstract: Voltage providing unit, voltage providing method, display driving module and display device are provided. The voltage providing unit, applied to a display panel, is configured to provide a control voltage signal for a driving circuit, and the voltage providing unit includes a buck circuit and a first electrical level converting circuit. The buck circuit is configured to receive a first voltage signal and perform a buck operation on the first voltage signal to obtain a second voltage signal; and the first electrical level converting circuit is connected to the buck circuit, and is configured to receive an input control voltage, a third voltage signal and the second voltage signal, and to generate the control voltage signal in accordance with the input control voltage, the third voltage signal and the second voltage signal, a voltage value of the control voltage signal is less than a predetermined voltage value.

Abstract: The present disclosure provides a TFT, a manufacturing method and a display substrate, and it relates to the field of TFT technology. The TFT includes: a base substrate; a gate electrode arranged on the base substrate; an active layer arranged at a side of the gate electrode away from the base substrate, an orthogonal projection of the active layer onto the base substrate overlapping with an orthogonal projection of the gate electrode onto the base substrate; and a source electrode and a drain electrode arranged at a side of the active layer away from the base substrate and coupled to the active layer. A resistance between the gate electrode and the drain electrode is greater than a resistance between the gate electrode and the source electrode. According to the present disclosure, it is able to increase a withstand voltage range of the TFT.

Abstract: The present disclosure provides an array substrate, a display panel, and a method for manufacturing the array substrate, belonging to the field of display technologies. In the array substrate, a first electrode having a higher voltage in the first electrode and a second electrode of the transistor is disposed between an active layer and a base in a lower lap manner, and the second electrode having a lower voltage is disposed on a first insulating layer in an upper lap manner or disposed below the first insulating layer in the lower lap manner. When the second electrode is disposed in the upper lap manner, the problem that the transistor cannot operate normally due to the too large resistance at the second electrode can be avoided.

Abstract: Provided is an array substrate. The array substrate includes: a substrate, multiple data lines disposed on a side of the substrate, multiple active patterns disposed on a side, distal to the substrate, of the multiple data lines, wherein the multiple active patterns correspond to the multiple data lines, and each active pattern includes a first conductive section and two second conductive sections disposed on two sides of the first conductive section, respectively, and the first conductive section of the active pattern is electrically connected to a data line corresponding to the first conductive section; and multiple pixel electrodes disposed on a side, distal to the substrate, of the multiple active patterns, wherein the two second conductive sections in the active pattern are electrically connected to two different pixel electrodes, respectively.

Abstract: Provided is a micro-nano fluidic substrate, a chip, a preparation method, and a system. The micro-nano fluidic substrate includes: a base; an electrode layer located on the base, the electrode layer includes a first electrode, a second electrode, and a control electrode; and a film layer located on the electrode layer and far away from the base, the film layer includes a groove layer, a nano-channel and a micro-channel, the groove layer includes a first groove, the nano-channel is located in the first groove, an orthographic projection of the nano-channel on the base at least partially coincides with an orthographic projection of the control electrode on the base, and the micro-channel is in communication with the nano-channel, the micro-channel includes a first micro-channel and a second micro-channel, and the first micro-channel is in communication with the first electrode, the second micro-channel is in communication with the second electrode.

Abstract: A display substrate and a display device are provided. The display substrate includes: a base substrate, and a low temperature poly-silicon thin film transistor and a metal oxide thin film transistor on the base substrate; the low temperature poly-silicon thin film transistor includes: a low temperature poly-silicon semiconductor layer, a first gate insulating layer, a first gate electrode, a first interlayer insulating layer, a first source electrode, and a first drain electrode; the metal oxide thin film transistor includes: a metal oxide semiconductor layer, a second gate insulating layer, a second gate electrode, a second interlayer insulating layer, a passivation layer, a second source electrode, and a second drain electrode; and the second drain electrode is on a side of the metal oxide semiconductor layer away from the base substrate.

Abstract: A driving backplane includes a first substrate, a thick copper layer, a second substrate, and a driving layer stacked in sequence. The thick copper layer is provided with a driving wire configured to load a driving signal. The driving layer is provided with a driving circuit. The driving circuit is electrically connected to the driving wire through a via.

Abstract: A thin-film transistor and an array substrate are provided. The thin-film transistor includes a substrate and an active layer on the substrate. The active layer includes multiple layers of oxides arranged in a stacked manner; the multiple layers of oxides include a channel layer, a transition layer, and a first barrier layer; the channel layer is a layer having the maximum carrier mobility in the multiple layers of oxides; the channel layer is a crystalline oxide layer or an amorphous oxide layer; the transition layer is in direct contact with the channel layer; the first barrier layer is the outermost oxide layer among the multiple layers of oxide; the first barrier layer and the transition layer are both crystalline oxide layers; the band gap of the first barrier layer and the band gap of the transition layer are both greater than the band gap of the channel layer.

Abstract: A functional backplane includes a wiring board, an intermetallic compound layer and a conductive connection layer. The wiring board includes a substrate, conductive pads and a plurality of protective layer groups. The conductive pads are disposed on the substrate and configured to transmit a driving signal. The plurality of protective layer groups are stacked on a side of the conductive pads away from the substrate. A protective layer group in the plurality of protective layer groups includes an oxidation protective layer, where a material of the oxidation protective layer includes a nickel-based alloy. In a direction perpendicular to the substrate and directed from the substrate to the protective layer group, the oxidation protective layer, the intermetallic compound layer and the conductive connection layer are stacked in sequence.

Abstract: A method for manufacturing a thin film transistor, and a thin film transistor are provided. The method includes: forming an active layer on a substrate by a single patterning process; forming a gate insulating layer by deposition on a side of the active layer away from the substrate; forming a first via hole and a second via hole penetrating through the gate insulating layer by a single patterning process, the first and second via holes being located at two ends of the active layer respectively; and forming a first electrode, a gate electrode, and a second electrode on the gate insulating layer by a single patterning process, the first and second electrodes being connected to the active layer through the first and second via holes, respectively, and an orthographic projection of the gate electrode on the substrate at least partially overlapping that of the active layer on the substrate.

Abstract: A wiring board includes a base substrate and first connection pads disposed on the base substrate. The first connection pads each include electrical connection layer(s); each electrical connection layer includes a main material layer and protective layer(s) disposed on a side of the main material layer away from the base substrate; the protective layer(s) include a first reference protective layer, which is a protective layer farthest away from the base substrate in the protective layer(s); and a material of the main material layer includes copper. The electrical connection layer(s) include a first electrical connection layer, which is an electrical connection layer farthest away from the base substrate in the electrical connection layer(s); and in protective layer(s) in the first electrical connection layer, at least a material of the first reference protective layer is capable of forming a first intermetallic compound with a first solder.

Abstract: A display substrate includes a base substrate and at least one transistor disposed on the base substrate, with a transistor including an active layer pattern disposed on the base substrate; a first source-drain electrode disposed on the base substrate and electrically connected with the active layer pattern; a first gate electrode disposed on a side of the active layer pattern away from the base substrate, the first gate electrode and the active layer pattern having overlapped orthographic projections on the base substrate and are not in contact with each other; a second source-drain electrode disposed on a side of the active lay pattern away from the base substrate and including a first sub-electrode and a second sub-electrode connected with each other, the second sub-electrode is located on a side of the first sub-electrode close to the first gate electrode, the first sub-electrode is electrically connected with the active layer pattern.