Abstract: A circuit board includes a substrate and a stress neutral layer disposed on a side of the substrate. The stress neutral layer includes one or more first metal layers and one or more second metal layers. The one or more second metal layers and the one or more first metal layers are stacked. At least one of the one or more first metal layers is made of a material for generating a tensile stress, and at least one of the one or more second metal layers is made of a material for generating a compressive stress.

Abstract: A display substrate and a manufacture method thereof, a display apparatus are provided. The display substrate includes a sub-pixel, the sub-pixel includes a pixel circuit, the pixel circuit includes a light-emitting device and a driving transistor, the driving transistor is configured to control a magnitude of a driving current flowing through the light-emitting device according to a data signal; the pixel circuit further includes a data transistor, the data transistor is configured to write the data signal into a first electrode of the driving transistor in response to a data driving signal; a material of an active layer of the driving transistor is a metal oxide semiconductor material, and a material of an active layer of the data transistor includes a silicon semiconductor material.

Abstract: A display substrate is provided. The display substrate includes a first substrate, a first insulating layer a first via hole, a semiconductor layer and a connecting electrode. The first via hole at least penetrates the first insulating layer and expos s a portion of a first signal line. The semiconductor laver includes a first portion, a second portion and a channel structure located between the first portion and the second portion. An orthogonal projection of the first portion on the first substrate partially overlaps with an orthogonal projection of the first signal line on the first substrate, and an orthogonal projection of the channel structure on the first substrate is located within an orthogonal projection of a first pattern on the first substrate. At least a portion of the connecting electrode is located in the first via hole and connected to the first portion and the first signal line.

Abstract: The present invention provides a pixel unit structure, in which a source electrode is connected to a data line in a thin film transistor; the gate electrode is connected to the gate line; the drain electrode is disposed on a side of the gate insulating layer away from the substrate; the metal oxide semiconductor layer is disposed on a side of the gate insulating layer away from the substrate, and includes a semiconductor portion and a first conductive portion and a second conductive portion respectively located on both sides of the semiconductor portion; a terminal of the first conductive portion adjacent to the drain electrode is connected to the drain electrode or serves as at least a portion of the drain electrode; and the second conductive portion is connected to the source electrode through a first via formed correspondingly on the gate insulating layer and the interlayer dielectric layer.

Abstract: A driving circuit and a display device are provided. The driving circuit includes a pull-up node noise reduction circuit, an input circuit, a first output noise reduction circuit and a pull-down node noise reduction circuit; at least one transistor included in the driving circuit is a floating processing transistor including a floating electrode, a gate electrode, a first electrode and a second electrode; the floating electrode is arranged on the same layer with at least one of the first electrodes and the second electrode of the floating processing transistor; the floating electrode is arranged between the first electrode and the second electrode of the floating processing transistor, and the floating electrode has no electric signal input; a shortest distance between the first electrode of the floating processing transistor and the second electrode of the floating processing transistor is greater than an initial distance.

Abstract: An array substrate has a display region and a peripheral region and includes a base substrate, a first signal line, a first transistor and a second transistor. The first signal line is disposed on the base substrate and at least partially located in the display region. The first transistor is located in the display region and disposed on a side of the first signal line away from the base substrate. The first transistor includes a first semiconductor pattern and a first gate disposed on a side of the first semiconductor pattern away from the base substrate. The second transistor is located in the peripheral region. The second transistor includes a second semiconductor pattern and a second gate disposed on a side of the second semiconductor pattern away from the base substrate; and the first gate and the second gate are arranged in a same layer.

Abstract: A semiconductor substrate manufacturing method and a semiconductor substrate. The manufacturing method includes: forming a first semiconductor layer on the base substrate at a first temperature with a first oxide semiconductor material; forming the second semiconductor layer directly on the first semiconductor layer with a second oxide semiconductor material; and performing a patterning process such that the first semiconductor layer and the second semiconductor layer are respectively patterned into a seed layer and a first channel layer. Both the first oxide semiconductor material and the second oxide semiconductor material are capable of forming crystalline phases at a second temperature, the second temperature is less than or equal to 40° C., and the first temperature is greater than or equal to 100° C.

Abstract: The present disclosure provides a display substrate, a method for manufacturing the display substrate and a display panel. The display substrate includes: a first semiconductor layer on a base substrate, where an active layer of the first thin film transistor is in the first semiconductor layer, and the active layer of the first thin film transistor at least comprises a channel region and a drain contact region; an interlayer insulation layer on a side of the first semiconductor layer away from the base substrate; and a first conductive layer on a side of the interlayer insulation layer away from the first semiconductor layer, wherein the pixel electrode is located in the first conductive layer, and the pixel electrode in the pixel unit is directly and electrically connected to the drain contact region of the active layer of the first thin film transistor through a through hole.

Abstract: Provided are a display substrate, display panel and display apparatus. The display substrate includes: a base substrate; a plurality of sub-pixels on a side of the base substrate, where each of the plurality of sub-pixels includes a sub-pixel opening region; an inorganic color-resist layer, on the same side as the plurality of sub-pixels, including a plurality of color-resist units, where an orthographic projection of the color-resist unit on the base substrate covers an orthographic projection of the sub-pixel opening region, and a light emitting color of the color-resist unit is same as a color of its corresponding sub-pixel; the color-resist unit includes at least two inorganic sub-layers stacked alternately, and different inorganic sub-layers have different refractive indexes.

Abstract: A display substrate and a display device. The display substrate includes a base substrate, and at least three functional layers, at least two first adaptation layers and a target connection member arranged on the base substrate. At least two functional layers of the at least three functional layers are laminated one on another in a direction away from the base substrate, and the at least three functional layers include a target functional layer. The at least two first adaptation layers include a top adaptation layer and at least one bottom adaptation layer, the top adaptation layer is arranged at a side of the target functional layer away from the base substrate, and at least a part of the bottom adaptation layer is arranged between the target functional layer and the base substrate.

Abstract: The present disclosure discloses an array substrate and a display device. The array substrate includes a base substrate (13) and a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer which are sequentially stacked on a side of the base substrate (13). The fourth conductive layer includes a common electrode (21), a material of the fourth conductive layer is a transparent conductive oxide material, a material of the third conductive layer is a metal conductive material, and at least a portion of a surface of the third conductive layer away from the base substrate (13) is in contact with at least a portion of a surface of the fourth conductive layer close to the base substrate (13).

Abstract: A thin film transistor includes a first electrode, a second electrode, an active layer, and a gate electrode disposed on a base substrate. The first electrode is located on a side of the active layer close to the base substrate, and a first insulation layer is disposed between the first electrode and the active layer, and is provided with a first via. The active layer is electrically connected to the first electrode through the first via. A second insulation layer is disposed between the gate electrode and the active layer. An orthographic projection of the gate electrode is overlapped, at least partially, with an orthographic projection of the first via, on the base substrate, a surface of a side of the gate electrode close to the base substrate is a first surface, a surface of a side of the gate electrode away from the base substrate is a second surface.

Abstract: The present disclosure provides a metal oxide thin film transistor, a semiconductor device and a display device, belongs to the field of display technology, and can solve a problem that current metal oxide thin film transistors have a poor stability. The metal oxide thin film transistor of the present disclosure includes a substrate and a first metal oxide semiconductor layer on the substrate; a material of the first metal oxide semiconductor layer includes a metal oxide doped with a first metal element, an electronegativity difference value between the first metal element and an oxygen element is greater than or equal to an electronegativity difference value between a metal element in the metal oxide and the oxygen element.

Abstract: An array substrate and a display device are provided. The array substrate includes a base substrate (12), and at least one transistor (11), at least one data line (DL) and at least one first electrode (10) disposed on the base substrate (12). The at least one transistor (11) includes an active layer (17), the active layer (17) includes two or more sub-active layers arranged in a stack, the two or more sub-active layers includes a first sub-active layer, the first sub-active layer is closer to the base substrate (12) than other sub-active layers. The first sub-active layer includes a first channel region (170-1) and a first sub-region (171-1) and a third sub-region (172-3) located on two opposite sides of the first channel region (170-1). The data line (DL) is electrically connected with the first sub-region (171-1), and the first electrode (10) is electrically connected with the third sub-region (172-3).

Abstract: There is provided a metal oxide thin film transistor, including: a substrate and a metal oxide semiconductor layer on the substrate; a gate and a gate insulating layer between the substrate and the metal oxide semiconductor layer; the gate insulating layer includes a first silicon nitride layer, a second silicon nitride layer and a first silicon oxide layer which are stacked; the first silicon oxide layer is in contact with the metal oxide semiconductor layer, and two surfaces of the second silicon nitride layer are in contact with the first silicon nitride layer and the first silicon oxide layer, respectively; a content of hydrogen atoms of at least a partial region of the second silicon nitride layer is less than 30% of a content of hydrogen atoms of at least a partial region of the first silicon nitride layer. An array substrate and a display device are further provided.

Abstract: A wiring board include a base substrate, an active pattern layer, and an electrical pattern layer. The active pattern layer is arranged on a side of the base substrate and includes a plurality of active patterns. The electrical pattern layer is arranged on a side of the active pattern layer away from the base substrate, and includes a plurality of connection portions, and at least one connection portion is coupled to an active pattern. A connection portion includes a plurality of first sub-layers which are stacked arranged in a thickness direction of the base substrate, two first sub-layers are farthest away from the base substrate among the plurality of first sub-layers are a first conductive sub-layer and a first protective sub-layer. The first protective sub-layer is arranged on a side of the first conductive sub-layer away from the base substrate, and the material of the first protective sub-layer includes nickel.

Abstract: Voltage providing unit, voltage providing method, display driving module and display device are provided. The voltage providing unit, applied to a display panel, is configured to provide a control voltage signal for a driving circuit, and the voltage providing unit includes a buck circuit and a first electrical level converting circuit. The buck circuit is configured to receive a first voltage signal and perform a buck operation on the first voltage signal to obtain a second voltage signal; and the first electrical level converting circuit is connected to the buck circuit, and is configured to receive an input control voltage, a third voltage signal and the second voltage signal, and to generate the control voltage signal in accordance with the input control voltage, the third voltage signal and the second voltage signal, a voltage value of the control voltage signal is less than a predetermined voltage value.

Abstract: The present disclosure provides a TFT, a manufacturing method and a display substrate, and it relates to the field of TFT technology. The TFT includes: a base substrate; a gate electrode arranged on the base substrate; an active layer arranged at a side of the gate electrode away from the base substrate, an orthogonal projection of the active layer onto the base substrate overlapping with an orthogonal projection of the gate electrode onto the base substrate; and a source electrode and a drain electrode arranged at a side of the active layer away from the base substrate and coupled to the active layer. A resistance between the gate electrode and the drain electrode is greater than a resistance between the gate electrode and the source electrode. According to the present disclosure, it is able to increase a withstand voltage range of the TFT.

Abstract: The present disclosure provides an array substrate, a display panel, and a method for manufacturing the array substrate, belonging to the field of display technologies. In the array substrate, a first electrode having a higher voltage in the first electrode and a second electrode of the transistor is disposed between an active layer and a base in a lower lap manner, and the second electrode having a lower voltage is disposed on a first insulating layer in an upper lap manner or disposed below the first insulating layer in the lower lap manner. When the second electrode is disposed in the upper lap manner, the problem that the transistor cannot operate normally due to the too large resistance at the second electrode can be avoided.

Abstract: Provided is an array substrate. The array substrate includes: a substrate, multiple data lines disposed on a side of the substrate, multiple active patterns disposed on a side, distal to the substrate, of the multiple data lines, wherein the multiple active patterns correspond to the multiple data lines, and each active pattern includes a first conductive section and two second conductive sections disposed on two sides of the first conductive section, respectively, and the first conductive section of the active pattern is electrically connected to a data line corresponding to the first conductive section; and multiple pixel electrodes disposed on a side, distal to the substrate, of the multiple active patterns, wherein the two second conductive sections in the active pattern are electrically connected to two different pixel electrodes, respectively.