Patents by Inventor Ce Ning

Ce Ning has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200185535
    Abstract: An oxide thin film transistor, an array substrate, and preparation methods thereof are disclosed. The method for preparing an oxide thin film transistor comprises a step of forming a pattern comprising an oxide semiconductor active layer on a substrate, wherein the step comprises: forming an amorphous oxide semiconductor thin film on the substrate; performing an excimer laser annealing, at least at a position in the amorphous oxide semiconductor thin film corresponding to a channel region of oxide semiconductor active layer to be formed, such that the amorphous oxide semiconductor material at the laser-annealed position is crystallized, to form a crystalline oxide semiconductor material; and forming the pattern comprising the oxide semiconductor active layer.
    Type: Application
    Filed: August 1, 2019
    Publication date: June 11, 2020
    Inventors: Feng Guan, Guangcai Yuan, Zhi Wang, Chen Xu, Qi Yao, Zhanfeng Cao, Ce Ning, Woobong Lee, Lei Chen
  • Patent number: 10629834
    Abstract: The present disclosure relates to the field of display, in particular to a thin film transistor, a method for preparing the same, and a display device. The thin film transistor of the present disclosure includes a gate electrode, a gate insulating layer, a semiconductor layer, a source electrode, a drain electrode, and a photoelectric conversion layer in contact with the gate electrode. The photoelectric conversion layer is configured to generate an induced potential in a light environment.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: April 21, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Song Liu, Yu Wen, Jianming Sun, Zhengliang Li, Xiaochen Ma, Hehe Hu, Wenlin Zhang, Jianhua Du, Ce Ning
  • Publication number: 20200119120
    Abstract: An array substrate includes a base substrate and a plurality of pixel units disposed on a base substrate, and at least one pixel unit includes a plurality of thin film transistors, a first electrode, and a second electrode. The plurality of thin film transistors include at least one first thin film transistor including a first active pattern, a first gate, a first source and a first drain. The first electrode is disposed in a same layer as the first active pattern, the first electrode is coupled to the first drain, and the second electrode is disposed in a same layer as the first gate. Orthographic projections of any two in a group consisting of the first electrode, the second electrode, and the first drain on the base substrate have an overlapping region.
    Type: Application
    Filed: December 12, 2019
    Publication date: April 16, 2020
    Inventors: Jing FENG, Dongsheng YIN, Ce NING, Jiushi WANG
  • Patent number: 10615284
    Abstract: The present disclosure provides a thin film transistor, a method for fabricating the same, a display substrate, and a display apparatus, and belongs to the field of display technology. The method includes: forming a metal oxide semiconductor pattern comprising first and second metal oxide semiconductor layers, the second metal oxide semiconductor layer being above the first metal oxide semiconductor layer; depositing a source-drain metal layer on the metal oxide semiconductor pattern; etching the source-drain metal layer and the second metal oxide semiconductor layer to form source and drain electrodes and an active layer of the thin film transistor. The active layer is obtained after removing the second metal oxide semiconductor layer between the source and drain electrodes using a first etchant, and the first etchant has a higher etching rate on the second metal oxide semiconductor layer than on the first metal oxide semiconductor layer.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: April 7, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Wei Yang, Ce Ning, Hehe Hu, Ke Wang
  • Publication number: 20200091263
    Abstract: The present discloses an array substrate and a manufacturing method thereof, and a display device. The array substrate includes a first transistor and a second transistor. The first transistor includes a first active layer, a first gate, a first source and a first drain. The second transistor includes a second active layer, a second gate, a second source and a second drain. An orthographic projection of the second source on the base substrate and an orthographic projection of the second drain on the base substrate at least partially overlap. One of the second source and the second drain is in the same layer as and made from the same material as the first gate. The first source and the first drain are in the same layer as and made from the same material as the other of the second source and the second drain.
    Type: Application
    Filed: August 30, 2019
    Publication date: March 19, 2020
    Inventors: Ke Wang, Xinhong Lu, Hehe Hu, Wei Yang, Ce Ning
  • Publication number: 20200066758
    Abstract: A display panel and a method for fabricating the same are provided.
    Type: Application
    Filed: August 5, 2019
    Publication date: February 27, 2020
    Inventors: Wei YANG, Guangcai YUAN, Ce NING, Xinhong LU
  • Patent number: 10510784
    Abstract: The present disclosure provides an array substrate and a method of manufacturing the same and a display apparatus in which the array substrate is applied. In one embodiment, the method of manufacturing an array substrate at least includes the steps of: forming a first electrode layer, a metal gate layer and a first layer of non-oxide insulation material, the first layer of non-oxide insulation material being formed on an upper surface of the metal gate layer; forming, by using one patterning process, a pattern including a first electrode and a gate such that, after completion of the patterning process, a first non-oxide insulation layer is further formed on the gate and a first sub-electrode belonging to the first electrode layer is further formed below the gate. This method of manufacturing the array substrate is simple, which facilitates mass production of the array substrate as well as the display apparatus.
    Type: Grant
    Filed: October 13, 2015
    Date of Patent: December 17, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Ce Ning, Fangzhen Zhang
  • Patent number: 10496868
    Abstract: An optical detector includes a stacked structure, an active layer, a gate insulating layer, and a gate electrode. The stacked structure includes a first electrode, a photoelectric conversion layer, a second electrode, a first insulating layer, and a third electrode. The active layer is electrically coupled to one of the first electrode or the second electrode, and electrically coupled to the third electrode. The gate insulating layer is arranged on the active layer. The gate electrode is arranged on the gate insulating layer.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: December 3, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Jianming Sun, Ce Ning, Wenlin Zhang
  • Patent number: 10483129
    Abstract: The disclosure discloses a method for roughening a surface of a metal layer, a thin film transistor, and a method for fabricating the same. The method for roughening the surface of a metal layer includes: forming a first photo-resist layer on the surface of the metal layer, and processing the first photo-resist layer at high temperature; and stripping the first photo-resist layer to roughen the surface of the metal layer.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: November 19, 2019
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Jing Feng, Seung Jin Choi, Fangzhen Zhang, Wusheng Li, Zhijun Lv, Ce Ning, Jiushi Wang
  • Patent number: 10431694
    Abstract: The present application discloses a thin film transistor including a base substrate; an active layer on the base substrate having a channel region, a source electrode contact region, and a drain electrode contact region; an etch stop layer on a side of the channel region distal to the base substrate covering the channel region; a source electrode on a side of the source electrode contact region distal to the base substrate; and a drain electrode on a side of the drain electrode contact region distal to the base substrate. A thickness of the active layer in the source electrode contact region and the drain electrode contact region is substantially the same as a combined thickness of the active layer in the channel region and the etch stop layer.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: October 1, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Ce Ning, Wei Yang
  • Patent number: 10403761
    Abstract: An array substrate and a manufacturing method thereof, and a display device are provided. The manufacturing method comprises: forming a first gate metal pattern on a base substrate; forming a gate insulating layer, a first active layer pattern and a source-drain metal pattern on the base substrate on which the first gate metal pattern is formed; forming a first protective layer pattern and a through hole pattern on the base substrate on which the source-drain metal pattern is formed; and forming a second active layer pattern and a pixel electrode pattern on the base substrate on which the first protective layer pattern is formed. Embodiments of the present disclosure solve problems of poor display performance and high cost of the array substrate and achieve effects of improving the display performance and reducing the cost.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: September 3, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Ce Ning, Wei Yang, Xiaohu Li
  • Publication number: 20190267559
    Abstract: The present disclosure relates to the field of display, in particular to a thin film transistor, a method for preparing the same, and a display device. The thin film transistor of the present disclosure includes a gate electrode, a gate insulating layer, a semiconductor layer, a source electrode, a drain electrode, and a photoelectric conversion layer in contact with the gate electrode. The photoelectric conversion layer is configured to generate an induced potential in a light environment.
    Type: Application
    Filed: August 28, 2018
    Publication date: August 29, 2019
    Inventors: Song Liu, Yu Wen, Jianming Sun, Zhengliang Li, Xiaochen Ma, Hehe Hu, Wenlin Zhang, Jianhua Du, Ce Ning
  • Publication number: 20190243497
    Abstract: Provided are an array substrate and preparation method therefor, and a display apparatus. The array substrate includes: a substrate, the substrate having a first TFT region, a touch control region and a second TFT region; a photosensitive PN junction, the photosensitive PN junction being provided in the touch control region; a first thin-film transistor, provided in the first TFT region, and electrically connected to the photosensitive PN junction; and a second thin-film transistor, provided in the second TFT region, and electrically connected to a pixel electrode.
    Type: Application
    Filed: May 14, 2018
    Publication date: August 8, 2019
    Inventors: Wenlin ZHANG, Wei YANG, Ce NING
  • Publication number: 20190233299
    Abstract: An oxide semiconductor composition for use in thin film transistors includes indium oxide, zinc oxide, and an oxide including a doping element of scandium, such as scandium oxide. A molar percentage of the indium oxide can be larger than approximately 50%. The oxide semiconductor composition can have a formula of In2Sc2ZnO7. Manufacturing of the oxide semiconductor composition can include: mixing indium oxide powder, scandium oxide powder, and zinc oxide powder to thereby obtain an oxide shaped object; and sintering the oxide shaped object to form the oxide semiconductor composition. A thin-film transistor for use in a semiconductor device, such as a display apparatus, can include the oxide semiconductor composition, and can thereby have improved mobility of the oxide semiconductor due to the reduced oxygen vacancy therein.
    Type: Application
    Filed: September 17, 2018
    Publication date: August 1, 2019
    Applicant: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Wenlin ZHANG, Ce NING, Hehe HU, Zhengliang LI
  • Patent number: 10332987
    Abstract: A thin film transistor, a manufacturing method for an array substrate, the array substrate, and a display device are provided. The manufacturing method for a thin film transistor includes: forming a semiconductor layer; performing a modification treatment on a surface layer of a region of the semiconductor layer, so that the region of the semiconductor layer has a portion in a first direction perpendicular to the semiconductor layer formed as an etching blocking layer, portions of the semiconductor layer on both sides of the etching blocking layer in a second direction parallel to a surface of the semiconductor layer remaining unmodified; and forming a source electrode and a drain electrode on the semiconductor layer, the source electrode and the drain electrode being formed on both sides of a center line of the region perpendicular to the second direction, and spaced from each other in the second direction.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: June 25, 2019
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Ce Ning, Wei Yang, Hehe Hu
  • Patent number: 10242886
    Abstract: A method for fabricating an array substrate is disclosed. The method comprises: forming a first oxide semiconductor active layer of a first TFT in a GOA area of a substrate; performing a first annealing process on the first oxide semiconductor active layer at a first temperature; forming a first insulating layer which covers the first oxide semiconductor active layer; performing a second annealing process on the first oxide semiconductor active layer at a second temperature, wherein the second temperature is lower than the first temperature. This improves a forward bias stability of the first TFT and increases the device lifetime.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: March 26, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Ce Ning, Wei Yang
  • Publication number: 20190051756
    Abstract: The present application discloses a thin film transistor including a base substrate; an active layer on the base substrate having a channel region, a source electrode contact region, and a drain electrode contact region; an etch stop layer on a side of the channel region distal to the base substrate covering the channel region; a source electrode on a side of the source electrode contact region distal to the base substrate; and a drain electrode on a side of the drain electrode contact region distal to the base substrate. A thickness of the active layer in the source electrode contact region and the drain electrode contact region is substantially the same as a combined thickness of the active layer in the channel region and the etch stop layer.
    Type: Application
    Filed: October 19, 2018
    Publication date: February 14, 2019
    Applicant: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Ce Ning, Wei Yang
  • Patent number: 10204997
    Abstract: The present application discloses a thin film transistor, a display substrate and display panel having the same, and a fabricating method thereof. The thin film transistor includes a base substrate; an active layer on the base substrate having a channel region, a first electrode contact region, and a second electrode contact region; and a first electrode on a side of the first electrode contact region distal to the base substrate; and a second electrode on a side of the second electrode contact region distal to the base substrate; the first electrode and the second electrode being made of an amorphous carbon material.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: February 12, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Ke Wang, Ce Ning
  • Patent number: 10192996
    Abstract: The present application discloses a thin film transistor including a base substrate; an active layer on the base substrate having a channel region, a source electrode contact region, and a drain electrode contact region; an etch stop layer on a side of the channel region distal to the base substrate covering the channel region; a source electrode on a side of the source electrode contact region distal to the base substrate; and a drain electrode on a side of the drain electrode contact region distal to the base substrate. A thickness of the active layer in the source electrode contact region and the drain electrode contact region is substantially the same as a combined thickness of the active layer in the channel region and the etch stop layer.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: January 29, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Ce Ning, Wei Yang
  • Publication number: 20190012508
    Abstract: An optical detector includes a stacked structure, an active layer, a gate insulating layer, and a gate electrode. The stacked structure includes a first electrode, a photoelectric conversion layer, a second electrode, a first insulating layer, and a third electrode. The active layer is electrically coupled to one of the first electrode or the second electrode, and electrically coupled to the third electrode. The gate insulating layer is arranged on the active layer. The gate electrode is arranged on the gate insulating layer.
    Type: Application
    Filed: September 5, 2017
    Publication date: January 10, 2019
    Applicant: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Jianming Sun, Ce Ning, Wenlin Zhang