Patents by Inventor Ce Ning

Ce Ning has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240276767
    Abstract: The present disclosure provides a display substrate, a preparing method therefor, and a display apparatus, the display substrate includes: a base substrate and a driving circuit layer arranged on the base substrate, the driving circuit layer further includes at least one first via hole, the first via hole is located between the second sub-electrode and the first active layer, an orthographic projection of the first via hole is overlapped with an orthographic projection of the first sub-electrode and an orthographic projection of the first active layer on the base substrate respectively, the first via hole exposes at least a portion of the first sub-electrode and at least a portion of the first active layer respectively, the second sub-electrode is electrically connected with the exposed first sub-electrode through the first via hole, and the second sub-electrode is electrically connected with the exposed first active layer through the first via hole.
    Type: Application
    Filed: May 31, 2022
    Publication date: August 15, 2024
    Inventors: Wei YANG, Ce NING, Lizhong WANG, Yunping DI, Tianmin ZHOU, Rui HUANG
  • Publication number: 20240261785
    Abstract: Provided is a micro-nano fluidic substrate, a chip, a preparation method, and a system. The micro-nano fluidic substrate includes: a base; an electrode layer located on the base, the electrode layer includes a first electrode, a second electrode, and a control electrode; and a film layer located on the electrode layer and far away from the base, the film layer includes a groove layer, a nano-channel and a micro-channel, the groove layer includes a first groove, the nano-channel is located in the first groove, an orthographic projection of the nano-channel on the base at least partially coincides with an orthographic projection of the control electrode on the base, and the micro-channel is in communication with the nano-channel, the micro-channel includes a first micro-channel and a second micro-channel, and the first micro-channel is in communication with the first electrode, the second micro-channel is in communication with the second electrode.
    Type: Application
    Filed: December 31, 2021
    Publication date: August 8, 2024
    Applicant: BOE Technology Group Co., Ltd.
    Inventors: Feifei Li, Bolin Fan, Ce Ning, Zhengliang Li, Hehe Hu, Nianqi Yao, Jiayu He, Jie Huang, Kun Zhao
  • Publication number: 20240266355
    Abstract: A display substrate and a display device are provided. The display substrate includes: a base substrate, and a low temperature poly-silicon thin film transistor and a metal oxide thin film transistor on the base substrate; the low temperature poly-silicon thin film transistor includes: a low temperature poly-silicon semiconductor layer, a first gate insulating layer, a first gate electrode, a first interlayer insulating layer, a first source electrode, and a first drain electrode; the metal oxide thin film transistor includes: a metal oxide semiconductor layer, a second gate insulating layer, a second gate electrode, a second interlayer insulating layer, a passivation layer, a second source electrode, and a second drain electrode; the second source electrode is on a side of the metal oxide semiconductor layer close to the base substrate; and the second drain electrode is on a side of the metal oxide semiconductor layer away from the base substrate.
    Type: Application
    Filed: March 23, 2022
    Publication date: August 8, 2024
    Inventors: Lizhong WANG, Ce NING, Wei YANG, Tianmin ZHOU, Liping LEI
  • Publication number: 20240255820
    Abstract: Provided is a substrate. The substrate includes a base substrate; and a plurality of sub-pixel structures arranged in an array on the base substrate, wherein the sub-pixel structure comprises: a thin film transistor disposed on the base substrate, the thin film transistor comprising a source and a drain; an insulating layer disposed on a side of the thin film transistor distal from the base substrate, a first via hole being formed in the insulating layer; a pixel electrode disposed on a side of the insulating layer distal from the base substrate, the pixel electrode being electrically connected to either the source or the drain through the first via hole; and a filling block disposed at the first via hole.
    Type: Application
    Filed: March 31, 2022
    Publication date: August 1, 2024
    Applicant: BOE Technology Group Co., Ltd.
    Inventors: Yunping DI, Lizhong WANG, Ce NING, Binbin TONG, Liping LEI, Jianbo XIAN
  • Publication number: 20240250177
    Abstract: A metal oxide thin film transistor is provided, which includes a metal oxide semiconductor layer, including a first semiconductor layer and a second semiconductor layer, the carrier mobility of the first semiconductor layer is higher than that of the second semiconductor layer; the metal oxide semiconductor layer includes a lower surface, an upper surface and a lateral surface, the source electrode is in contact with the lateral surface and the upper surface; the region where the lateral surface contacts the source electrode or the drain electrode includes a first contact region and a second contact region; which have the shape: a first angle between the lower surface of the metal oxide semiconductor layer and the lateral surface of the first contact region is larger than a second angle between the lower surface of the metal oxide semiconductor layer and the lateral surface of the second contact region.
    Type: Application
    Filed: March 31, 2022
    Publication date: July 25, 2024
    Applicant: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Dapeng XUE, Lizhong WANG, Shuilang DONG, Hehe HU, Nianqi YAO, Guangcai YUAN, Ce NING, Zhengliang LI, Dongfang WANG, Liping LEI, Chen XU, Jie HUANG
  • Publication number: 20240250178
    Abstract: The present disclosure provides a metal oxide thin film transistor, an array substrate and a display device. A metal oxide thin film transistor in the present disclosure includes: a substrate, a first metal oxide semiconductor layer on the substrate, and a second metal oxide semiconductor layer on a side of the first metal oxide semiconductor layer away from the substrate; a carrier mobility of the first metal oxide semiconductor layer is higher than that of the second metal oxide semiconductor layer; a material of the first metal oxide semiconductor layer includes: a first metal oxide doped with a rear earth element; a difference between an electronegativity of the rare earth element and an electronegativity of oxygen element is greater than or equal to a difference between an electronegativity of a metal element in the first metal oxide and the electronegativity of oxygen element.
    Type: Application
    Filed: February 17, 2022
    Publication date: July 25, 2024
    Inventors: Jiayu HE, Kun ZHAO, Yan QU, Liping LEI, Ce NING, Zhengliang LI, Hehe HU
  • Publication number: 20240243206
    Abstract: A thin film transistor; includes a substrate; and a semiconductor layer provided on the substrate. The semiconductor layer includes a first surface proximate to the substrate and a second surface away from the substrate, and the semiconductor layer is made of a metal oxide semiconductor material. The semiconductor layer has a channel region; and crystals of metal oxide semiconductor are formed at least in the channel region of the semiconductor layer and proximate to the first surface or the second surface.
    Type: Application
    Filed: August 27, 2021
    Publication date: July 18, 2024
    Inventors: Guangcai Yuan, Lingyan Liang, Hongtao Cao, Fengjuan Liu, Ce Ning, Fei Wang, Hehe Hu, Xiaolong Wang
  • Publication number: 20240244747
    Abstract: A wiring board includes a base substrate and first connection pads disposed on the base substrate. The first connection pads each include electrical connection layer(s); each electrical connection layer includes a main material layer and protective layer(s) disposed on a side of the main material layer away from the base substrate; the protective layer(s) include a first reference protective layer, which is a protective layer farthest away from the base substrate in the protective layer(s); and a material of the main material layer includes copper. The electrical connection layer(s) includes a first electrical connection layer, which is an electrical connection layer farthest away from the base substrate in the electrical connection layer(s); and in protective layer(s) in the first electrical connection layer, at least a material of the first reference protective layer is capable of forming a first intermetallic compound with a first solder.
    Type: Application
    Filed: December 31, 2021
    Publication date: July 18, 2024
    Inventors: Nianqi YAO, Feifei LI, Ce NING, Zhengliang LI, Hehe HU, Jiayu HE, Jie HUANG, Kun ZHAO, Zhanfeng CAO, Ke WANG
  • Publication number: 20240241415
    Abstract: An array substrate and a display panel. The array substrate includes: a base substrate; a gate line and a data line on the base substrate, the gate line intersect the data line to define a pixel region; a metal oxide thin film transistor is arranged in the pixel region, the metal oxide thin film transistor includes a metal oxide semiconductor layer; the metal oxide semiconductor layer includes a first part and a second part; the first part and the data line are connected through a first via hole; the first part is in a stripe shape; a first included angle is between extension directions of the first part and the data line; an orthographic projection of the second part overlap with an orthographic projection of the gate line on the base substrate and do not overlap with an orthographic projection of the data line on the base substrate.
    Type: Application
    Filed: January 10, 2023
    Publication date: July 18, 2024
    Applicant: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Lizhong WANG, Guangcai YUAN, Ce NING, Jianbo XIAN, Liping LEI, Chunping LONG, Yunping DI, Binbin TONG, Zhen ZHANG
  • Patent number: 12041825
    Abstract: An organic electroluminescent display substrate is provided, which includes a base substrate, and a light-emitting unit and a light-sensing unit arranged on the base substrate, wherein the light-sensing unit is arranged on a light-emitting side of the light-emitting unit, and configured for sensing an intensity of light emitted from the light-emitting unit; a first planarization layer is arranged between the light-sensing unit and the light-emitting unit; the light-sensing unit comprises a first thin film transistor and a photosensitive sensor arranged sequentially in that order in a direction away from the base substrate, and a second planarization layer is arranged between the photosensitive sensor and the first thin film transistor. A display panel, a display device and a method for manufacturing the organic electroluminescent display substrate are further provided.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: July 16, 2024
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Jiayu He, Ce Ning, Zhengliang Li, Hehe Hu, Jie Huang, Nianqi Yao, Xue Liu
  • Publication number: 20240234532
    Abstract: The present disclosure provides a TFT, a manufacturing method and a display substrate, and it relates to the field of TFT technology. The TFT includes: a base substrate; a gate electrode arranged on the base substrate; an active layer arranged at a side of the gate electrode away from the base substrate, an orthogonal projection of the active layer onto the base substrate overlapping with an orthogonal projection of the gate electrode onto the base substrate; and a source electrode and a drain electrode arranged at a side of the active layer away from the base substrate and coupled to the active layer. A resistance between the gate electrode and the drain electrode is greater than a resistance between the gate electrode and the source electrode. According to the present disclosure, it is able to increase a withstand voltage range of the TFT.
    Type: Application
    Filed: December 27, 2021
    Publication date: July 11, 2024
    Inventors: Hehe HU, Dongfang WANG, Fengjuan LIU, Ce NING, Zhengliang LI, Jiayu HE, Yan QU, Kun ZHAO, Jie HUANG, Liping LEI, Yunsik IM, Shunhang ZHANG, Nianqi YAO, Feifei LI
  • Publication number: 20240234658
    Abstract: A wiring board includes a substrate, conductive pads and at least one protective layer group. The conductive pads are disposed on the substrate. The at least one protective layer group is disposed on a side of the conductive pads away from the substrate; a protective layer group includes an oxidation protective layer and a palladium alloy layer that are stacked, and the oxidation protective layer is closer to the substrate than the palladium alloy layer. A material of the oxidation protective layer includes a nickel-based alloy.
    Type: Application
    Filed: December 29, 2021
    Publication date: July 11, 2024
    Applicant: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Jiayu HE, Yan QU, Ce NING, Zhengliang LI, Hehe HU, Jie HUANG, Nianqi YAO, Kun ZHAO, Feifei LI, Qi QI
  • Publication number: 20240221851
    Abstract: The present disclosure provides a shift register unit, a gate driving circuit and a display device. The shift register unit provided by the present disclosure includes: an input sub-circuit, an output sub-circuit, at least one pull-down control sub-circuit, at least one pull-down sub-circuit, at least one first noise reduction sub-circuit, and a reverse bias sub-circuit; the reverse bias sub-circuit is configured to control transistors in at least part of sub-circuits connected to a pull-up node to be in a reverse bias state through a power voltage signal in response to a potential of the pull-up node, or control the transistors in at least part of the sub-circuits connected to the pull-up node to be in the reverse bias state through a cascade signal in response to a potential of a cascade signal terminal.
    Type: Application
    Filed: November 30, 2021
    Publication date: July 4, 2024
    Inventors: Yunsik IM, Shunhang ZHANG, Fuqiang LI, Changfeng LI, Liwei LIU, Hehe HU, Ce NING, Hui ZHANG, Hongrun WANG, Zhuo LI
  • Publication number: 20240222445
    Abstract: A thin film transistor, an array substrate and a manufacturing method of the thin film transistor are provided, the thin film transistor includes a base substrate; and a first active layer, a first insulating layer and a second active layer, which are sequentially arranged on the base substrate, the first active layer is in contact with the second active layer through a first via hole structure located in the first insulating layer, and non-contacted portions of the first active layer and the second active layer are separated by the first insulating layer, the thin film transistor has a plurality of active layer structures, so that the charges are gathered on two surfaces of each of the active layers, and the number of the charges gathered on the surfaces of the active layers is multiplied, and the open state current of the thin film transistor is multiplied.
    Type: Application
    Filed: November 3, 2021
    Publication date: July 4, 2024
    Inventors: Jie HUANG, Ce NING, Zhengliang LI, Hehe HU, Nianqi YAO, Kun ZHAO, Tianmin ZHOU, Liping LEI
  • Publication number: 20240215332
    Abstract: The present disclosure provides a display substrate and a preparation method thereof, and a display apparatus. The display substrate includes a circuit layer disposed on a base substrate, an emitting structure layer and a photoelectric structure layer disposed on a side of the circuit layer away from the base substrate, the circuit layer includes at least one impurity absorption layer and at least one transistor, the transistor includes an active layer, and at least one insulation layer is provided between the impurity absorption layer and the active layer; an atomic ratio of a silicon element to a nitrogen element in the impurity absorption layer is 1:5 to 1:35.
    Type: Application
    Filed: November 4, 2021
    Publication date: June 27, 2024
    Inventors: Jiayu HE, Ce NING, Zhengliang LI, Hehe HU, Fengjuan LIU, Wei LIU, Tianmin ZHOU, Kun ZHAO
  • Publication number: 20240212773
    Abstract: The present disclosure provides a shift register unit, and driving method therefor, a gate drive circuit, and a display device, belonging to the field of display technologies. The shift register unit includes an input circuit, a compensation control circuit, and an output circuit. The input circuit can control a potential of a first node under control of an input signal provided by an input signal terminal and control a potential of a reference node under control of the input signal and an input control signal provided by an input control terminal. The compensation control circuit can adjust the potential of the first node based on the potential of the reference node under control of a first clock signal provided by a first clock signal terminal. In this way, the flexibility of controlling the first node is improved. Thus, the output circuit can flexibly output a drive signal to an output terminal coupled to a gate line under control of the first node.
    Type: Application
    Filed: October 25, 2021
    Publication date: June 27, 2024
    Inventors: Fengjuan LIU, Ce NING, Wei LIU, Dini XIE, Yuhang LU
  • Publication number: 20240212564
    Abstract: A display substrate, a manufacturing method thereof and a display apparatus are provided. In the present disclosure, a first transistor group with oxide semiconductor as an active layer material is disposed on a side of a second transistor group with polysilicon as an active layer material away from the base, and an area enclosed by orthographic projections of the transistors in the first transistor group on the base is overlapped with an area enclosed by orthographic projections of the transistors in the second transistor group on the base. Stable performance of the transistors included can be ensured in a manufacturing process of the first transistor group and the second transistor group located in different layers, and at the same time, an area occupied by the driving circuit can be reduced so as to decrease a frame width of a display apparatus or improve resolution of the display apparatus.
    Type: Application
    Filed: November 4, 2021
    Publication date: June 27, 2024
    Applicant: BOE Technology Group Co., Ltd.
    Inventors: Lizhong Wang, Ce Ning, Yunping Di, Binbin Tong, Chengfu Xu, Dapeng Xue, Shuilang Dong, Nianqi Yao
  • Publication number: 20240212639
    Abstract: Voltage providing unit, voltage providing method, display driving module and display device are provided. The voltage providing unit, applied to a display panel, is configured to provide a control voltage signal for a driving circuit, and the voltage providing unit includes a buck circuit and a first electrical level converting circuit. The buck circuit is configured to receive a first voltage signal and perform a buck operation on the first voltage signal to obtain a second voltage signal; and the first electrical level converting circuit is connected to the buck circuit, and is configured to receive an input control voltage, a third voltage signal and the second voltage signal, and to generate the control voltage signal in accordance with the input control voltage, the third voltage signal and the second voltage signal, a voltage value of the control voltage signal is less than a predetermined voltage value.
    Type: Application
    Filed: September 24, 2021
    Publication date: June 27, 2024
    Inventors: Shuilang DONG, Ce NING, Guangcai YUAN, Hehe HU, Lizhong WANG, Nianqi YAO, Dapeng XUE, Liping LEI, Chen XU, Dongfang WANG, Zhengliang LI
  • Publication number: 20240204004
    Abstract: Provided are a thin-film transistor and a manufacturing method thereof, and a display substrate, belonging to the technical field of thin-film transistors. The thin-film transistor includes: a base substrate; a gate electrode on the base substrate; an active layer on a side of the gate electrode away from the base substrate, an orthographic projection of the active layer onto the base substrate overlapping with an orthographic projection of the gate electrode onto the base substrate; and a first electrode and a second electrode on a side of the active layer away from the base substrate, the first electrode being one of a source electrode and a drain electrode, and the second electrode being the other of the source electrode and the drain electrode.
    Type: Application
    Filed: December 27, 2021
    Publication date: June 20, 2024
    Inventors: Hehe HU, Yan QU, Jiayu HE, Kun ZHAO, Jie HUANG, Zhengliang LI, Ce NING, Dongfang WANG, Fengjuan LIU, Nianqi YAO, Feifei LI, Shunhang ZHANG, Yunsik IM, Liping LEI
  • Publication number: 20240204002
    Abstract: Embodiments of the present disclosure provide an array substrate and method for manufacturing same, a display panel, and a display device, and relate to the field of display technologies. The array substrate includes a color filter layer, such that a distance between a light source on a side, distal from the color filter layer, of the base substrate and the color filter layer is less. Thus, light from regions of the color resist blocks is avoided being emitted from adjacent color resist blocks, and a cross color of the display panel is further avoided, such that the display effect of the display panel is great. In addition, the color resist block is at least partially overlapped with a second portion of a metal oxide pattern in an oxide thin film transistor, such that an overall footprint of the oxide thin film transistor and the color filter layer can be reduced, so as to acquire the display panel of high PPI.
    Type: Application
    Filed: October 28, 2021
    Publication date: June 20, 2024
    Inventors: Zhen ZHANG, Fuqiang LI, Zhenyu ZHANG, Lizhong WANG, Yunping DI, Ce NING, Zheng FANG, Chenyang ZHANG, Yawei WANG, Wei WANG, Hongrun WANG, Binbin TONG, Nianqi YAO, Jiahui HAN, Chengfu XU, Pengxia LIANG