Cecil H. Kaplinsky has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
Abstract: A multiprocessor computer system in which each processor being used as a target device has a FIFO (first in first out) buffer for receiving and storing transfer commands from a split transactional global bus for later execution. The transfer commands are put in the FIFO of the target device in the order of their arrival and are taken out of the FIFO and executed by the target device in the same order. This eliminates the wasting of bus time that occurs when busy signals are sent from target devices to master devices and when transfer commands are resent from master devices to target devices. Therefore, the present invention eliminates the wasting of bus time related to transfer commands being rejected.
Abstract: Configurable I/O circuitry having a plurality of configurable input/output elements, each of which connects one of a plurality of bits of a data bus to a corresponding one of the input/output terminals. Multiple clock selects and programmable enable signals can be connected to different interface elements to control activation of the interface element to which it is connected. The activated interface elements make up a virtual port that can be of any arbitrary bit width that is less than or equal to the fixed width of a physical port. This allows virtual ports on the data bus to be constructed that are narrower than the physical ports so that narrower data can be utilized in the port without causing the potential use of any of the data pins to be lost.
Abstract: A low power, static content addressable memory having combinatorial logic gates to connect the selection lines of a plurality of memory cells in a manner that does not compromise the stability of the cells. In one embodiment, each memory cell has one set of complementary bit lines, while in a second embodiment, each memory cell has two or more sets of bit lines to allow simultaneous read operations or simultaneous read and write operations. Because precharging of the selection line is not required, the memory consumes less power in operation.
Abstract: In a system of plural bus driver circuits connected to a shared bus line, each of the driver circuits has combinatorial logic responsive, driving a final clock cycle for an active driver, to the difference between the data input and output of a tri-state driver element so as to generate a control signal that maintains the driver element in a active state until the data input and output are identical and then providing early release of the driver element to an inactive state, so that the next driver circuit can be activated at the start of the next clock cycle without conflict.
Abstract: A digital interface circuit has two inverters with different switching points, one below and one above the nominal transition point of the circuit. Each inverter controls both pull-up and pull-down output transistors. The inverter with the low switching point controls the low-to-high signal transition, while the inverter with the high switching point controls the high-to-low signal transition. Pass gates responsive through delay elements to either the circuit input, an inverter output, or the circuit output isolate the other inverter from the output transistors. The pass gates may also be tristatable by means of a logical combination of the delayed pass gate enable signals with output enable signals. In yet another embodiment, the pair of inverters are replaced by a single inverter with dual switching points.
Abstract: A first output buffer circuit with independent transparent latch and tristate output capabilities includes input translators that directly drive a pair of main pull-up and pull-down output transistors. The input translators are tristatable in response to latch control signals and latching elements on side branches of the signal paths leading from the translator outputs to the output transistor gates hold the last voltage value on those signal paths at the time the translators are disabled. The main current paths through the output transistors include isolation transistors in series with the output transistors and responsive to feedback control from the buffer output. These feedback paths include logic gates responsive to output enable control signals that can shut off isolation transistors and hence put the buffer output in a high impedance state.
Abstract: A programmable logic device in accordance with the present invention includes a partially populated switch matrix for coupling a plurality of logic blocks. Having a partial switch matrix reduces the silicon area requirement of the device. In addition, the capacitive loading is reduced, which improves propagation speed and lowers the power requirement of the sense amps, since smaller sense amps can be used. Bypass means are provided to allow the propagation bit lines (i.e. carry and shift lines) to bypass one or more logic block. Each of the logic blocks includes a plurality of logic cells. Means are provided among the logic cells to provide bypass capability for the propagation lines among the logic cells. The logic cells feature means for reverse propagation of the carry and shift bits among the logic cells. The logic cells of the present invention also feature reverse propagation with bypass.
Abstract: A dynamic termination circuit is disclosed that has a plurality of parallel termination elements that respond successively to a signal transition and which are selectively enabled and disabled to provide a desired impedance match with a transmission line. Each termination element includes a first dynamic resistive path between a voltage supply line and that termination element's output and a second dynamic resistive path between the termination element output and ground, both resistive paths including field-effect transistors whose control gates are responsive to a signal received from the transmission line via an input to the circuit. For successive response, a series of delay elements are provided between the circuit input and the respective termination circuit elements. For selective enablement, logic gates connected between the termination element inputs and the field-effect transistor control gates have enable inputs receiving user-programmable enable signals for the respective termination elements.
Abstract: A buffer circuit includes a pair of pull-up output transistors and a pair of pull-down output transistors driving an output line. Each output transistor is driven by its own tristate input translator, all connected to an input terminal of the circuit. Two of the translators are tristated by control signals received as feedback from the output line to turn off one of the pull-up transistors when the output exceeds the high logic level transition voltage (2.2 V) and to turn off one of the pull-down transistors when the output drops below the low logic level transition voltage (0.8 V). This not only prevents ground bounce or overshoot of the output, but also avoids larger current flow or power dissipation from pull-up and pull-down transistors being simultaneously partially on during a transition.
Abstract: A buffer, driver, or level-shifting circuit having an input connected to signal inputs of a pair of comparators and an output connected between a pair of pull-up and pull-down transistors controlled by the comparators. A first reference voltage applied to the reference input of the comparator controlling the pull-up transistor is selected to be less than the nominal transition point of the circuit, while a second reference voltage applied to the reference input of the comparator controlling the pull-down transistor is selected to be greater than the nominal transition point of the circuit, thereby allowing the circuit to recognize the beginning of signal transitions on the its input sooner. The comparators are differential amplifiers which are enableable and disableable in response to a feedback signal from the circuit's output in order to reduce current consumption during transitions.
Abstract: A non-volatile memory connected to state logic is provided for autoloading peripheral target devices at power-on or system reset. The memory is preloaded with commands and data. At power-on or system reset the commands are executed in sequence, transferring data to selected target devices. Data is output in bit-serial fashion on a single line. Target devices are individually selected through use of separate clock lines. Clock signals on the clock lines can be internally generated using the state logic or a target-device-supplied clock can be received under program selection. The system reset signal is intercepted and retransmitted to control target device mode. System reset polarity, enable signal polarity, data block length, clock direction, internal clock frequency, and power-saving shutdown upon completion of all transfers are all programmably selectable features.
Abstract: A logic circuit having a programmable first logic circuit stage and a fixed or dedicated combinatorial second logic circuit stage, serving as a macrocell for the first logic circuit stage. At least one input to the logic circuit is connected directly to the second stage, bypassing the first stage. The first stage may be a programmable logic device with a programmable AND plane followed by an OR plane, and is functionally flexible. The second stage has at least two groups of CMOS logic gates arranged in sequence and connected in a fixed manner by hardwiring so as to implement a specified combinatorial logic function that is representable in sum-of-products form, and is fast compared to the first stage. The outputs from the first stage control logic operations of the second stage upon the directly connected input or inputs.
Abstract: A digital logic circuit for use in or as a macrocell which can be programmed to operate as a flip-flop or as a latch, or to be transparent to a signal, and which also has programmable output polarity. This programmable macrocell circuit has two master latch elements and one slave latch element. The master latch elements are respectively inverting and noninverting latches which are located on two parallel alternate paths. A set of pass transistors on the input end of the two paths causes an input signal to drive only a selected one of the two paths and its associated master latch element. A two-by-one multiplexer connects the output of the selected master latch element in one of the two signal paths to the input of the slave latch.
Abstract: A write assist circuit for CMOS inverter-type memory cells and latches having means for choking current flow from a voltage level source to power supply terminals of a group of such memory cells or latches during a data loading or write cycle. The write assist circuit has a pair of pass transistors that respectively connect to one or two voltage level sources. In one embodiment, both pass transistors connect in parallel to a single voltage level source, one transistor always active being of low conductance, the other transistor of normal conductance being turned off by a write enable signal. In another embodiment, both pass transistors are of normal conductance but are respectively enabled and disabled by a write enable signal and are connected to different voltage level sources so as to supply a lower power supply voltage to the CMOS inverter-type memory cells or latches during a write cycle.
Abstract: A clock distribution circuit with multiple clock drivers distributing a clock signal on multiple signal paths has active de-skewing logic circuitry for equalizing the total clock delay to the different clock recipient circuits in a system. The de-skewing logic uses a return path parallel to the outward signal path to sense the propagation delay and includes a phase comparator with inputs receiving the return signal and a reference signal for comparison of their phase. Voltage-controlled delay elements, responsive to a control voltage provided by a charge pump controlled by the phase comparator, adds or removes equal amounts of delay to the outward and return signal paths until the return signal phase matches that of the reference signal. Each clock driver may have its own de-skewing circuitry or may share a common reference signal.
Abstract: A low power logic array and a programmable logic device made up of two successive logic arrays, at least one of which being a low power array, in which the programmable elements in the array are multibit memory elements. Logic gates combine the outputs of corresponding memory elements. The logic array includes a set of array inputs which may be arranged in groups connecting to decoder inputs. Decoder outputs provide an address signal to address inputs of the memory elements. In a preferred embodiment, the memory elements are arranged in a matrix of rows and columns with each row connected to a decoder and each column coupling to one or more logic gates. The logic gates may be AND, OR, NAND or NOR gates, and may be arranged in a hierarchy of successive stages of logic gates.
Abstract: A CMOS flip-flop circuit that includes master and slave inverter latches, a pass transistor for opening and closing access of the master latch input to an input signal D, and a special driver circuit between the master and slave latches to pull the input of the slave latch either up or down depending on the logic level of the master latch output. The pass transistor and driver circuit are responsive to a control signal, supplied by complementary clock signals or by multiplexers that select either the clock signals or a fixed logic high signal, to activate a conductive path to the inputs of respective master and slave latches. The driver circuit includes four transistors connected, so that first and second transistors are in series and third and fourth transistors are in series, to form two parallel paths from two logic level sources to the slave latch input.
Abstract: An input/output (I/O) processor and data processing system in which the processor receives and services interrupt request signals from I/O controllers, which requests may be internally or externally coded, and supervises blockwise transfer of data between an external memory associated with a main processing unit and the I/O controllers. The I/O processor includes an internal memory for storing information pertinent to data transfer from each I/O channel including the address where channel programs, decision tables and data buffers are maintained in external memory. A sequencer executes a specialized instruction set which includes instructions that invoke an interpretation means enabling examination of status registers of the I/O controllers and/or data values therefrom and the branching of execution based thereon.
March 23, 1989
Date of Patent:
July 14, 1992
North American Philips Corp., Signetics Div.
Abstract: A programmable logic device having a plurality of functional units, a programmable interconnect matrix for connecting the functional units together, input and output pins coupled to the interconnect matrix, and programmable inverters connected between the pins and conductive lines of the matrix to permit external signals leading into or out of the interconnect matrix to be inverted, if desired. Each functional unit may itself be a programmable logic device with inputs, an AND array connected to the inputs, an OR array connected to the AND array, optional registers and inverters on the output side of the OR array, and outputs coupled to the OR array, the registers or the inverters. The programmable interconnect matrix includes two sets of conductive lines crossing one another and connectable by programmable links at each intersection. The lines connect to functional unit inputs and to input and output pins.
Abstract: A programmable logic device architecture having a matrix of smaller functional units, each of which being a programmable logic array, and a set of fixed conductive lines connected to the functional unit inputs and outputs, the conductive lines forming programmable interconnection matrices. The input pins can be programmably connected to any input of any functional unit, and the outputs of functional units can be programmably connected to any input of any functional unit or any output pin. The interconnection matrices may be a simple array of crossing conductive lines with crossings connected by fuses, EPROM, or EEPROM switches or may have additional series switches to limit the effective impedance so as to speed propagation through these matrices. A fast path through one functional unit bypassing the interconnection matrices is available for a limited number of input and output pins.