Abstract: A programmable logic device architecture having a matrix of smaller functional units, each of which being a programmable logic array, and a set of fixed conductive lines connected to the functional unit inputs and outputs, the conductive lines forming programmable interconnection matrices. The input pins can be programmably connected to any input of any functional unit, and the outputs of functional units can be programmably connected to any input of any functional unit. Output pins connect directly to outputs of functional units. The interconnection matrices may be a simple array of crossing conductive lines with crossings connected by EPROM, or EEPROM switches.

Abstract: Apparatus for programming an OR gate, an AND gate or an EXCLUSIVE-OR gate to accept or not accept an input signal at an input terminal of the gate. The apparatus includes two pass transistors, a source of high or low voltage depending on the gate to be programmed, and a control signal that is used for programming the gates of the pass transistors. The two pass transistors may be of the same channel type i.e.,. both n-channel or both p-channel, or they may be of opposite channel types. This apparatus provides positive input signals from a group of input signals to avoid voltage signal ambiguities in programming the gates. Use of these programmable gates in combination in an AND-OR array is illustrated.

Abstract: A programmable logic device that provides an AND gate array connected to an OR gate array connected to a third logic level, a logic expander module. The module provides programmable selection of any of 16 one- and two-variable logic functiosn or any of 256 one-, two- and three-variable logic functions. In one embodiment, the invention uses logic function gates such as AND, OR, XOR and inverter gates to form the logic functions. In a second embodiment and a third embodiment, a look-up table and an array of pass transistors, respectively, are used to form the logic functions.

Abstract: A configuration control circuit in an integrated circuit device, such as a programmable logic device, having a programmable memory for storing configuration bits and one or more shift registers which are loadable from the memory. The memory is an array of nonvolatile memory cells that can be user programmed with data corresponding to a desired device architecture. The shift registers are loaded with this data upon power up or a reset. The registers in combination with other circuit gates control the operation of the device such that a particular architecture is implemented. The various configurations can be tested without altering the contents of the memory by loading the shift register externally.

Abstract: Because a customary data processing apparatus consisting of a program control section, an arithmetic and logic element and a data memory, also referred to as a microprocessor or microcontroller when integrated on a semiconductor chip, is temporarily not loaded by a control function in many applications, it is desirable to perform a plurality of such slow control functions by means of one apparatus. In order to achieve this as effectively as possible, in accordance with the invention there are added a sequencer and an address memory which is controlled by the sequencer and which takes up each time the next instruction address of a given control function or process which is each time associated with a sequence control signal. FOr the arithmetic and logic element there is preferably provided a buffer memory which is also controlled by the sequencer.

Abstract: A programmable logic device architecture having a matrix of smaller functional units, each of which being a programmable logic array, and a set of fixed conductive lines connected to the functional unit inputs and outputs, the conductive lines forming programmable interconnection matrices. The input pins can be programmably connected to any input of any functional unit, and the outputs of functional units can be programmably connected to any input of any functional unit or any output pin. The interconnection matrices may be a simple array of crossing conductive lines with crossings connected by fuses, EPROM, or EEPROM switches or may have additional series switches to limit the effective impedance so as to speed propagation through these matrices. A fast path through one functional unit bypassing the interconnection matrices is available for a limited number of input and output pins.

Abstract: In a bit-mapped display system, a logical subsystem for programmable sharing of access to a memory in a computer system among a plurality of system resources wherein various modes of operation are supported by the logic and are programmably selected by the user. The use of display memory is controlled between updating and display accesses to prevent breakup of the video image while said image is being changed.

Abstract: In a virtual memory system, a guarded region allows access to protected code and data without intervention from a processor's operating system by redefining regions of an address space with reference to gates indicating points of entry for those regions. A non-hierarchial access path in the form of a tree-like structure permits a process to access resources and data while controlling access thereto and return therefrom.

Abstract: The data processing system of the invention comprises a processor, a memory access controller and a memory hierarchy. The memory access controller is placed between the processor and the memory hierarchy and controls access thereto. The memory access controller comprises a cache controller and a translation unit which are connected in parallel to an address bus connected to the processor and by which virtual addresses are transported. The memory access controller supports segments which are unit of sharing the memory, each segment is split up into pages. The memory access controller also supports regions which contain at least one segment. The memory access controller further supports sectors, divided into blocks which are other units of sharing the memory. And the memory access controller is also provided for enabling access with I/O units.

Abstract: A device for the interrogation and correction of a data signal which adopts a finite number of discrete signal values in a consecutive series of data cells. The transitions between the signal values exhibit a nominal minimum spacing. The signal is periodically interrogated with a period which amounts to, at the most, half of said minimum spacing. If a finite series of successive interrogation values exhibits a permissible pattern, the data value is directly derived therefrom (36). There is a set of further patterns which are not permissible, but which do not deviate excessively from a permissible pattern; the associated data value of the corresponding permissible pattern is then simulated. In the other cases an error signal (34) is formed. The pattern has a length which exceeds the length of a data cell. The inherent redundancy of the data signal is thus partly used for the correction of errors.

Abstract: For a communication system for the transmission of digital information over a bus channel using pulses having a considerably different pulse length for the transmission of "0" and "1" bits, respectively. In the preferred embodiment the length of a "0" pulse is at least 2.1 times longer than the length of a "1" to pulse, so that the tolerance on detection of the reception has ample room to absorb wide tolerances in the frequency of a RC-clock generator, e.g. .+-.25%, for propagation time delays and for any inaccuracy in the moment of detection when pulse edges of low steepness must be used.

Abstract: A data processing machine having a device for extending the length of the logic address to (M+N) bits, so that 2.sup.M+N different logic addresses can be formed and become available to the programmer. The original data structure of a computer having a word length of only N bits is then maintained. Programs written for the original machine can be executed without modification. A register bank of a data processing machine having its extension has a first section having a width of N bits which forms the least-significant side or tail, and a second section which has a width of M bits and which forms the more significant side or head. The first section is used in all instructions which utilize an operand from a register or which store an operand in a register, in the same manner as in the computer without the extension.