Abstract: First processing circuitry processes at least part of a stream of program instructions. The first processing circuitry has registers for storing data and register renaming circuitry for mapping architectural register specifiers to physical register specifiers. A renaming data store stores renaming entries for identifying a register mapping between the architectural and physical register specifiers. At least some renaming entries have a count value indicating a number of speculation points occurring between generation of a previous count value and generation of the count value. The speculation points may for example be branch operation or load/store operations.

Abstract: A data processing apparatus 2 supports speculative execution and the use of sticky bits. A different version of a sticky bit is associated with each segment of the speculative program flow. The segments of the program flow are separated by speculation nodes corresponding to program instructions which may be followed by a plurality of different alternative program instruction serving as the next program instruction. When a speculation node is resolved, then the segments separated by that speculation node are merged and the sticky bit values for those two segments are merged.

Abstract: Within a processing pipeline 14, issue control circuitry 12 serves to arbitrate write port availability when floating point multiplication instructions are issued into a floating point pipeline 14. If not operating in a flush-to-zero mode, then depending upon the output operands generated denormal handling may or may not be required. A pessimistic assumption is made upon issue that denormal handling will be required and accordingly the write port reserved is a first predetermined number of processing cycles after the start cycle to take account of use of the denormal handling pipeline stage 20. Partway along the processing pipeline 14, state becomes available which indicates whether or not denormal handling is actually required. If denormal handling is not required and a write port is available one processing cycle earlier, then bypass circuitry 22 serves to bypass the denormal handling pipeline stage 20 such that the output operand will be written to the register bank 16 one processing cycle earlier.

Abstract: Data storage circuitry for securely storing confidential data and a data processing apparatus for processing and storing the data and a method are disclosed. The data storage circuitry comprises: a data store comprising a plurality of data storage locations for storing data; an input for receiving requests to access the data store; renaming circuitry for mapping architectural data storage locations specified in the access requests to physical data storage locations within the data store; encryption circuitry for encrypting data prior to storing the data in the data store, the encryption circuitry being configured to generate an encryption key in dependence upon a physical data storage location the data is to be stored in; and decryption circuitry for decrypting data read from the data store, the decryption circuitry being configured to generate a decryption key in dependence upon the physical data storage location the data is read from.

Abstract: The data processing apparatus (and method) has processing circuitry for performing data processing operations in response to data processing instructions, the data processing instructions referencing logical registers. A set of physical registers are provided for storing data values for access by the processing circuitry when performing the data processing operations. Register renaming storage stores a one-to-one mapping between the logical registers and the physical registers, with the register renaming storage being accessed by the processing circuitry when performing the data processing operations in order to map the referenced logical registers to corresponding physical registers. Update circuitry is arranged to identify the physical registers corresponding to those multiple logical registers in the register renaming storage. Altered one-to-one mapping between multiple logical registers and identified physical registers is employed when performing the current data processing operation.

Abstract: A data processing apparatus comprises first and second processing circuitry. A conditional instruction executed by the second processing circuitry may have an outcome which is dependent on one of a plurality of sets of condition information maintained by the first processing circuitry. A first forwarding path can forward the sets of condition information from the first processing circuitry to a predetermined pipeline stage of a processing pipeline of the second processing circuitry. A request path can transmit a request signal from the second processing circuitry to the first processing circuitry, the request signal indicating a requested set of condition information which was not yet valid when a conditional instruction was at the predetermined pipeline stage. A second forwarding path may forward the requested set of condition information to a subsequent pipeline stage when the information becomes valid.

Abstract: Register renaming circuitry for a processing apparatus configured to process a stream of instructions from an instruction set specifying registers from an architectural set of registers. The apparatus including a physical set of registers configured to store data values being processed by the processing apparatus. Register renaming circuitry is configured to receive a stream of operations from an instruction decoder and to map registers that are to be written to by the stream of operations to physical registers within the physical set of registers that are currently available. The register renaming circuitry comprises register release circuitry configured to release the physical registers that have been mapped to the registers when a first set of conditions have been met, and to release the physical registers that have been mapped to the additional registers when a second set of conditions have been met.

Abstract: An apparatus and method includes execution circuitry including a wide operand execution unit configured to allow up to N bits of operand data to be processed during execution of a single instruction. Decoder circuitry decodes and generates, for each instruction, at least one control data block identifying an operation to be performed by the execution circuitry and at least two re-combineable control data blocks for the instruction. Issue queue control circuitry then allocates a slot in the issue queue for each of the at least two data blocks and up to M bits of associated operand data, and marks those allocated slots to identify that they contain re-combineable control data blocks. The issue queue control circuitry issues the combined block to said wide operand execution unit along with the operand data contained in each of the allocated slots for said at least two control data blocks.

Abstract: First processing circuitry processes at least part of a stream of program instructions. The first processing circuitry has registers for storing data and register renaming circuitry for mapping architectural register specifiers to physical register specifiers. A renaming data store stores renaming entries for identifying a register mapping between the architectural and physical register specifiers. At least some renaming entries have a count value indicating a number of speculation points occurring between generation of a previous count value and generation of the count value. The speculation points may for example be branch operation or load/store operations.

Abstract: A data processing apparatus comprises first and second processing circuitry. A conditional instruction executed by the second processing circuitry may have an outcome which is dependent on one of a plurality of sets of condition information maintained by the first processing circuitry. A first forwarding path can forward the sets of condition information from the first processing circuitry to a predetermined pipeline stage of a processing pipeline of the second processing circuitry. A request path can transmit a request signal from the second processing circuitry to the first processing circuitry, the request signal indicating a requested set of condition information which was not yet valid when a conditional instruction was at the predetermined pipeline stage. A second forwarding path may forward the requested set of condition information to a subsequent pipeline stage when the information becomes valid.

Abstract: Within a processing pipeline 14, issue control circuitry 12 serves to arbitrate write port availability when floating point multiplication instructions are issued into a floating point pipeline 14. If not operating in a flush-to-zero mode, then depending upon the output operands generated denormal handling may or may not be required. A pessimistic assumption is made upon issue that denormal handling will be required and accordingly the write port reserved is a first predetermined number of processing cycles after the start cycle to take account of use of the denormal handling pipeline stage 20. Partway along the processing pipeline 14, state becomes available which indicates whether or not denormal handling is actually required. If denormal handling is not required and a write port is available one processing cycle earlier, then bypass circuitry 22 serves to bypass the denormal handling pipeline stage 20 such that the output operand will be written to the register bank 16 one processing cycle earlier.

Abstract: A data processing apparatus 2 supports speculative execution and the use of sticky bits. A different version of a sticky bit is associated with each segment of the speculative program flow. The segments of the program flow are separated by speculation nodes corresponding to program instructions which may be followed by a plurality of different alternative program instruction serving as the next program instruction. When a speculation node is resolved, then the segments separated by that speculation node are merged and the sticky bit values for those two segments are merged.

Abstract: The data processing apparatus (and method) has processing circuitry for performing data processing operations in response to data processing instructions, the data processing instructions referencing logical registers. A set of physical registers are provided for storing data values for access by the processing circuitry when performing the data processing operations. Register renaming storage stores a one-to-one mapping between the logical registers and the physical registers, with the register renaming storage being accessed by the processing circuitry when performing the data processing operations in order to map the referenced logical registers to corresponding physical registers. Update circuitry is arranged to identify the physical registers corresponding to those multiple logical registers in the register renaming storage. Altered one-to-one mapping between multiple logical registers and identified physical registers is employed when performing the current data processing operation.

Abstract: Clock signal control circuitry is disclosed along with a method for switching a clock between modes and a computer program product. The clock signal control circuitry is for receiving a clock signal from a clock signal generator and for outputting said clock signal to synchronous circuitry that is to be clocked by said clock signal.

Abstract: Data storage circuitry for securely storing confidential data and a data processing apparatus for processing and storing the data and a method are disclosed. The data storage circuitry comprises: a data store comprising a plurality of data storage locations for storing data; an input for receiving requests to access the data store; renaming circuitry for mapping architectural data storage locations specified in the access requests to physical data storage locations within the data store; encryption circuitry for encrypting data prior to storing the data in the data store, the encryption circuitry being configured to generate an encryption key in dependence upon a physical data storage location the data is to be stored in; and decryption circuitry for decrypting data read from the data store, the decryption circuitry being configured to generate a decryption key in dependence upon the physical data storage location the data is read from.

Abstract: A data processing apparatus is configured to perform a data processing operation on at least one data value in response to a data processing instruction. The data processing apparatus comprises a delay unit situated on a path within the data processing apparatus, wherein the delay unit is configured to apply a delay to propagation of a signal on the path and propagation of that signal forms part of the data processing operation. The data processing apparatus is configured to determine a result of the data processing operation at a predetermined time point, wherein the predetermined time point following an initiation of the data processing operation by a predetermined time interval. The delay unit is configured such that a time for the data processing operation to be performed plus the delay is less than the predetermined time interval.

Abstract: A data processing apparatus and method are provided for executing complex instructions. The data processing apparatus executes instructions defining operations to be performed by the data processing apparatus, those instructions including at least one complex instruction defining a sequence of operations to be performed. The data processing apparatus comprises a plurality of execution pipelines, each execution pipeline having a plurality of pipeline stages and arranged to perform at least one associated operation. Issue circuitry interfaces with the plurality of execution pipelines and is used to schedule performance of the operations defined by the instructions. For the at least one complex instruction, the issue circuitry is arranged to schedule a first operation in the sequence, and to issue control signals to one of the execution pipelines with which that first operation is associated, those control signals including an indication of each additional operation in the sequence.

Abstract: Within a data processing system including a register renaming mechanism, register renaming for some conditional instructions which are predicted as not-executed is suppressed. The conditional instructions which are subject to such suppression of renaming may not be all conditional instructions, but may be those which are known to consume a particularly large number of physical registers if they are subject to renaming A conditional load multiple instruction in which multiple registers are loaded with new data values taken from memory in response to a single instruction is an example where the present technique may be used, particularly when one of the registers loaded is the program counter and accordingly the instruction is a conditional branch.

Abstract: Cache logic is provided for use in a data processing apparatus, the cache logic having a cache storage comprising a plurality of cache lines for storing data values. Control logic is arranged, in response to an access request issued by a device of the data processing apparatus identifying a memory address of the data value to be accessed, to cause a lookup operation to be performed to determine whether the data value for that memory address is stored within the cache storage. The control logic is further operable if the data value is not stored in the cache storage to perform a linefill process, the linefill process comprising performing an eviction to evict to memory of the data processing apparatus current content of a selected cache line, keeping the current content valid in the selected cache line whilst the eviction is taking place, and storing from the memory into the selected cache line new content including the data value the subject of the access request.

Abstract: A processor 2 utilising register renaming executes program instructions requiring a large number of architectural register specifiers to be renamed by dividing the renaming tasks into an initial set and a remaining set. The initial set are performed first and the results passed via a main channel 32 for further processing. The remaining set are performed in sequence with the results being passed via a background channel 34 for further processing. This technique is particularly useful for performing renaming operations for load/store multiple LDM instructions.