Abstract: Clock signal control circuitry is disclosed along with a method for switching a clock between modes and a computer program product. The clock signal control circuitry is for receiving a clock signal from a clock signal generator and for outputting said clock signal to synchronous circuitry that is to be clocked by said clock signal.

Abstract: A data processing apparatus processes a stream of instructions from an instruction set. The instruction set includes exception instructions and non-exception instructions. Exception instructions may cause a break in an instruction flow, and non-exception instructions execute in a statically determinable way. At least two processing blocks process instructions from the stream of instructions. A first processing block has a set of physical registers associated with it for storing data values being processed by the first processing block. Renaming circuitry associated with the first processing block maps architectural registers specified in instructions to be processed by the first processing block to physical registers within the set of physical registers. A second processing block has a set of physical registers associated with it for storing data values being processed by the second processing block. The second processing block and registers do not support renaming.

Abstract: A data processing apparatus 2 supports out-of-order processing register renaming using a renaming stage 8. A set of physical registers 16 is mapped to architectural registers. Available-register identifying logic 26 is used to identify which physical registers 16 are available for use by the renaming stage 8. The available-register identifying logic 26 includes an instruction FIFO 28 storing register mapping data for unresolved instructions and indicating physical registers 16 storing data values which may be required in association with those unresolved speculative instructions. The speculative instructions may be predicted branch instructions, load/store instructions, conditional instructions or other types of instruction.

Abstract: A data processing apparatus and a method for caching data values in data processing apparatus comprising a level one cache and a level two cache is disclosed. Both the level one cache and the level two cache are operable to store the data values. The method comprises the steps of: a) receiving a transaction request in which a data transaction relating to a data value is requested to occur, the transaction request including cache policy attributes associated with an address of the data value; and b) determining from the cache policy attributes whether or not the data value can be stored by the level one cache and the level two cache and, if so, in which one of the level one cache and the level two cache the data value is to be stored in order to ensure that the data value is prevented from being stored in both the level one cache and the level two cache.

Abstract: A data processing apparatus and method are provided for executing complex instructions. The data processing apparatus executes instructions defining operations to be performed by the data processing apparatus, those instructions including at least one complex instruction defining a sequence of operations to be performed. The data processing apparatus comprises a plurality of execution pipelines, each execution pipeline having a plurality of pipeline stages and arranged to perform at least one associated operation. Issue circuitry interfaces with the plurality of execution pipelines and is used to schedule performance of the operations defined by the instructions. For the at least one complex instruction, the issue circuitry is arranged to schedule a first operation in the sequence, and to issue control signals to one of the execution pipelines with which that first operation is associated, those control signals including an indication of each additional operation in the sequence.

Abstract: The present invention provides a data processing apparatus and method for managing cache memories. The data processing apparatus comprises a processing unit for issuing an access request seeking access to a data value, and a hierarchy of cache memories for storing data values for access by the processing unit. The hierarchy of cache memories comprises at least an n-th level cache memory and n+1-th level cache memory which at least in part employ exclusive behavior with respect to each other. Each cache memory comprises a plurality of cache lines, at least one dirty value being associated with each cache line, and each dirty value being settable to indicate that at least one data value held in the associated cache line is more up-to-date than a corresponding data value stored in a main memory.

Abstract: Within a data processing system 2 including a register renaming mechanism 8, 22, register renaming for some conditional instructions which are predicted as not-executed is suppressed. The conditional instructions which are subject to such suppression of renaming may not be all conditional instructions, but may be those which are known to consume a particularly large number of physical registers 24 if they are subject to renaming A conditional load multiple instruction in which multiple registers are loaded with new data values taken from memory in response to signal instruction is an example where the present technique may be used, particularly when one of the registers loaded is the program counter and accordingly the instruction is a conditional branch.

Abstract: A data processing apparatus operable to process a stream of instructions from an instruction set, said instruction set comprising exception instructions and non-exception instructions, exception instructions being instructions that may cause a break in an instruction flow and non-exception instructions being instructions that execute in a statically determinable way, said data processing apparatus comprising: at least two processing blocks for processing instructions from said stream of instructions; a first processing block having a set of physical registers associated with it for storing data values being processed by said first processing block, renaming circuitry associated with said first processing block for mapping architectural registers specified in instructions to be processed by said first processing block to physical registers within said set of physical registers; a second processing block having a set of physical registers associated with it for storing data values being processed by said second

Abstract: A data processing apparatus 2 supports out-of-order processing register renaming using a renaming stage 8. A set of physical registers 16 is mapped to architectural registers. Available-register identifying logic 26 is used to identify which physical registers 16 are available for use by the renaming stage 8. The available-register identifying logic 26 includes an instruction FIFO 28 storing register mapping data for unresolved instructions and indicating physical registers 16 storing data values which may be required in association with those unresolved speculative instructions. The speculative instructions may be predicted branch instructions, load/store instructions, conditional instructions or other types of instruction.

Abstract: Cache logic is provided for use in a data processing apparatus, the cache logic having a cache storage comprising a plurality of cache lines for storing data values. Control logic is arranged, in response to an access request issued by a device of the data processing apparatus identifying a memory address of the data value to be accessed, to cause a lookup operation to be performed to determine whether the data value for that memory address is stored within the cache storage. The control logic is further operable if the data value is not stored in the cache storage to perform a linefill process, the linefill process comprising performing an eviction to evict to memory of the data processing apparatus current content of a selected cache line, keeping the current content valid in the selected cache line whilst the eviction is taking place, and storing from the memory into the selected cache line new content including the data value the subject of the access request.

Abstract: A processor 2 utilising register renaming executes program instructions requiring a large number of architectural register specifiers to be renamed by dividing the renaming tasks into an initial set and a remaining set. The initial set are performed first and the results passed via a main channel 32 for further processing. The remaining set are performed in sequence with the results being passed via a background channel 34 for further processing. This technique is particularly useful for performing renaming operations for load/store multiple LDM instructions.

Abstract: Control logic for storing values relating to unresolved exception instructions within a buffer to enable a register renaming table within a processor to be restored following an exception is disclosed. The processor is operable to process a stream of instructions from an instruction set, the instruction set comprising exception instructions and non-exception instructions, exception instructions being instructions that may generate an exception and non-exception instructions being instructions that execute in a statically determinable way.