Abstract: A method of performing instruction scheduling during execution in a processor includes receiving, at an execution unit of the processor, an initial assignment of an assigned execution resource among two or more execution resources to execute an operation. An instruction includes two or more operations. Based on determining that the assigned execution resource is not available, the method also includes determining, at the execution unit, whether another execution resource among the two or more execution resources is available to execute the operation. Based on determining that the other execution resource is available, the method further includes executing the operation with the other execution resource.

Abstract: A method includes obtaining a trigger signal directed to a component in a subset of components of an electronic circuit, and activating a clock corresponding with the subset of components of the electronic circuit for a preliminary period in response to the trigger signal. An active period is determined based on the trigger signal. The clock remains active for the active period. One of a timer or counter is initiated for the active period. A limit is defined for the one of the timer or counter. The active period is dynamically extended for a busy period after the one of the timer or counter is initiated. The clock is deactivated following the active period.

Abstract: Aspects include parsing, by a computer system, a design file of an integrated circuit including a plurality of stages to extract a plurality of inputs and outputs of a plurality of latches. The computer system can sort the latches based on latch locations in the stages and build a plurality of ordered vectors of signals before and after the latches based on the sorting. The computer system can build a plurality of parity vectors for each of the ordered vectors of signals before and after the latches, build a latch bank for each of the parity vectors before the latches, and build a parity vector comparison to detect a parity failure based on comparing the parity vectors after the latches with an output of the latch bank.

Abstract: A substring can be detected within a string of data elements through a method that includes partitioning and distributing the string of data elements to an ordered list of segments having equal lengths greater than or equal to the length of the substring. A substring match within a segment of the ordered list of segments can be detected by sequentially comparing the substring with each segment of the ordered list of segments. A carry vector that includes the substring match can be created, in response to detecting the substring match that is a partial match. It can be determined that a carry vector exists by comparing the substring with the segment of the ordered list of segments, and it can be subsequently determined that a full match exists between the carry vector and the segment of the ordered list of segments.

Abstract: A method, computer program product and/or system is disclosed. According to an aspect of this invention, a device under test (DUT) is switched to a functional test mode. In some embodiments of the present invention, the DUT receives a general scan design (GSD) pattern while in the functional test mode. In some embodiments, the DUT executes a first functional test corresponding to the GSD pattern. In yet other embodiments, the DUT further comprises a state machine that controls the execution of the first functional test. The DUT may further store the output address, the output data, and the status to an address register, a data register, and a status register, respectively and/or send the output address, the output data, and the status to an address register to an automatic testing equipment (ATE).

Abstract: A method for dynamically selecting a size of a memory access may be provided. The method comprises accessing blocks having a variable number of consecutive cache lines, maintaining a vector with entries of past utilizations for each block size, and adapting said block size before a next access to the blocks.

Abstract: Digit validation check control for execution of an instruction. A process obtains an instruction to perform operation(s) using input value(s). The instruction includes a no validation indicator for controlling whether digit validation check control is enabled for execution of the instruction. The process executes the instruction, including determining, based on the no validation indicator, whether digit validation check control is enabled for execution of the instruction, and performing processing based on the determining. Based on the no validation indicator being set to a defined value, digit validation check control is enabled and the processing includes forcing a digit check error indicator output by the executing to indicate no digit check error with respect to the at least one input value.

Abstract: Negative zero control for execution of an instruction. A process obtains an instruction to perform operation(s) using an input value. The instruction includes a negative zero control indicator indicating whether negative zero control is enabled for execution of the instruction. The process executes the instruction, the executing including performing the operation(s) using the input value to obtain a result having a sign, determining whether to control the sign of the result, the determining being based at least in part on the negative zero control indicator being set to a defined value, and performing further processing, as part the executing the instruction, based on the determining.

Abstract: An instruction is provided for performing a vector string search. The instruction to be processed is obtained, with the instruction being defined to be a string search instruction to locate occurrence of a substring within a string. The instruction is processed, with the processing including searching the string specified in one operand of the instruction using the substring specified in another operand of the instruction. Based on the searching locating a first full match of the substring within the string, a full match condition indication is returned with position of the first full match in the string, and based on the searching locating only a partial match of the substring at a termination of the string, a partial match condition indication is returned, with the position of the partial match in the string.

Abstract: A single architected instruction to perform a data reversal operation is executed. The executing includes obtaining input data and a modifier control of the instruction. The modifier control has one value of a plurality of values defined for the instruction and indicates an element size. The data reversal operation is performed on the input data. The performing includes placing, in a selected location, an element of the input data, the element having the element size indicated by the modifier control; reversing an order of the input data in the element; and repeating the placing and the reversing, based on the input data having one or more other elements to be processed. The output of the performing includes one or more elements of data that include output data in a reversed order from the input data of the corresponding one or more elements.

Abstract: A single architected instruction to perform a data reversal operation is executed. The executing includes obtaining input data and a modifier control of the instruction. The modifier control has one value of a plurality of values defined for the instruction and indicates an element size. The data reversal operation is performed on the input data. The performing includes placing an element of the input data in a selected location in reverse element order from an order of the element in the input data, the element having the element size indicated by the modifier control. The placing is repeated, based on the input data having one or more other elements to be processed. The output of the performing includes one or more elements of data in the selected location in a reversed order from the corresponding one or more elements in the input data.

Abstract: Aspects include a method for logic built-in self-testing (LBIST) for use in an integrated circuit with scan chains. The method includes programming a product control generator and a pattern generator with an LBIST pattern comprising at least a number of loops. The LBIST pattern is executed by generating scan-in test values for scan chains with the pattern generator and controlling at least one test parameter with the product control generator. Scan-out responses are collected from the scan chains in a signature register, and a start request is received from a chip tester. The LBIST is started in response to the start request. Test summary data is reported to the chip tester before the whole number of loops has been executed.

Abstract: A processor unit can rapidly search a string of characters. The processor unit includes vector registers each having M vector elements, each having n bits of data for containing an encoded character. An M×M matrix of comparators within the processor unit can be used to compare elements of a first register storing a reference string and elements of a second register storing a target string. A logic gate is associated with each upper diagonal of the matrix of comparators and is configured to combine the results of comparators along the diagonal, resulting in a bit vector indicating characters of the target string that fully match the reference string and characters that partially match the reference string. The processor unit result generating logic generates, using the resulting bit vector, an indication of a substring of the target string that matches a fragment of the reference string.

Abstract: A method, computer program product, and computer system for providing a comparison result vector of a predefined number of elements w resulting from comparison of multiple vectors of compressed data within a processor comprising registers of same size m is provided. Vector elements of the comparison result vector are stored in a register of the registers. Zero bits are padded between vector elements of each of the comparison result vectors. A compare bit result vector indicative of the vector elements is generated for accessing the results of the comparison in the comparison result vector.

Abstract: Aspects include a system having logic built-in self-test (LBIST) circuitry for use in an integrated circuit with scan chains. The system includes a pattern generator configured for generating scan-in test values for said scan chains; a signature register configured for collecting scan-out responses from said scan chains after a clock sequence; an on-product control generator configured for controlling at least one test parameter; one or more microcode array or memory elements configured to receive inputs to initialize fields in the microcode array or memory elements; and a test controller. The test controller includes a reader component configured for reading test parameters from a field of the microcode array or the memory elements; and a programming component configured for configuring the on-product control generator and the pattern generator with a LBIST pattern according to the read test parameters.

Abstract: Instruction interrupt suppression for an overflow condition. An instruction is executed, and a determination is made that an overflow condition occurred. Based on a per-instruction overflow interrupt indicator being set to a defined value, interrupt processing for the overflow condition is performed, and based on the per-instruction overflow interrupt indicator being set to another defined value, the interrupt processing for the overflow condition is bypassed.

Abstract: A number of non-overlapping instances of a substring occurring within a string of data elements can be determined through a method that includes partitioning and distributing the string to an ordered list of equal length segments that each have a length greater or equal to L. A substring match within a target segment of the ordered list of segments can be detected by sequentially comparing the substring with each segment of the ordered list of segments. It can be subsequently determined that the target segment contains additional data elements, and a new segment can be generated by clearing L?1 data elements following a position of the substring match in the target segment. An additional substring match can be detected by comparing the substring with the new segment.

Abstract: A system, apparatus, and method of testing a plurality of test circuits is disclosed that includes inputting experiment data to the plurality of test circuits; applying a control signal to each of the plurality of test circuits to control application of the experiment data to the plurality of test circuits; and shifting the control signal in response to applying the control signal to each of the plurality of test circuits so that a different bit of the control signal is applied to each of the plurality of test circuits. The method in an aspect further comprises reading out a data out signal from each of the plurality of test circuits; and shifting the data out signal in response to reading out the data out signal from each of the plurality of test circuits.

Abstract: The present disclosure relates to a method for instruction processing with a processor having multiple execution units. The processor includes a dependency cache containing instructions in association with respective execution unit indicators. The method includes: tracking the number of dependent instructions currently assigned to each execution unit of the processor respectively. In response to receiving an instruction of a dependency chain, the execution unit assigned to a previous instruction of the dependency chain on which depends the received instruction may be identified in the dependency cache. In case more than a predefined maximum number of dependent instructions of at least one dependency chain is currently assigned to the identified execution unit, another execution unit of the processor may be selected for scheduling the received instruction, otherwise the received instruction may be scheduled on the identified execution unit.

Abstract: Aspects include a method for logic built-in self-testing (LBIST) for use in an integrated circuit with scan chains. The method includes programming a product control generator and a pattern generator with an LBIST pattern comprising at least a number of loops. The LBIST pattern is executed by generating scan-in test values for scan chains with the pattern generator and controlling at least one test parameter with the product control generator. Scan-out responses are collected from the scan chains in a signature register, and a start request is received from a chip tester. The LBIST is started in response to the start request. Test summary data is reported to the chip tester before the whole number of loops has been executed.