Abstract: Checking a computer processor design for soft error handling. A baseline simulation of a computer processor design is monitored to identify a target processing cycle of the baseline simulation during which a predefined event occurs during the baseline simulation. The baseline simulation is performed in accordance with a software model of the computer processor design, and the event is associated with processing an instruction that directly involves a predefined error injection target. A test simulation of the computer processor design is performed in accordance with the software model of the computer processor design. An error is injected into the predefined error injection target during a target processing cycle of the test simulation. A determination is made as to whether the error is detected by error-checking logic of the computer processor design.

Abstract: Checking a computer processor design for soft error handling. A baseline simulation of a computer processor design is monitored to identify a target processing cycle of the baseline simulation during which a predefined event occurs during the baseline simulation. The baseline simulation is performed in accordance with a software model of the computer processor design, and the event is associated with processing an instruction that directly involves a predefined error injection target. A test simulation of the computer processor design is performed in accordance with the software model of the computer processor design. An error is injected into the predefined error injection target during a target processing cycle of the test simulation. A determination is made as to whether the error is detected by error-checking logic of the computer processor design.

Abstract: A processor with multiple execution units for instruction processing is provided. The processor comprises an instruction decode and issue logic and a control logic for resolving register access conflicts between subsequent instructions and a dependency cache, which comprises a receiving logic for receiving an execution unit indicator indicative of the execution unit the instruction is planned to be executed on, a storing logic responsive to the receiving logic for storing the received execution unit indicator, and a retrieving logic responsive to a request from the instruction decode and issue logic for providing the stored execution unit indicator for an instruction. The instruction decode and issue logic is adapted for requesting execution unit indicator for an instruction from the dependency cache and to assign the instruction to one respective of the execution units dependent on the execution unit indicator received from the dependency cache.

Abstract: Disclosed herein is a computer implemented method for performing multiply-add operations of binary numbers P, Q, R, S, B in an arithmetic unit of a processor, the operation calculating a result as an accumulated sum, which equals to B+n×P×Q+m×R×S, where n and m are natural numbers. Further disclosed herein is an arithmetic unit configured to implement multiply-add operations of binary numbers P, Q, R, S, B comprising at least a first binary arithmetic unit for calculating an aligned high part result and a second binary arithmetic unit for calculating an aligned low part result of the multiply-add operations.

Abstract: A circuit includes reconfigurable units that are reconfigurable to compute a combined result. A first intermediate result of a first reconfigurable unit of the reconfigurable units is exchanged with a second intermediate result of the second reconfigurable unit of the reconfigurable units. The first reconfigurable unit computes a first portion of the combined result utilizing the second intermediate result. The second reconfigurable unit of the reconfigurable units computes a second portion of the combined result utilizing the first intermediate result.

Abstract: A method for dynamically selecting a size of a memory access may be provided. The method comprises accessing blocks having a variable number of consecutive cache lines, maintaining a vector with entries of past utilizations for each block size, and adapting said block size before a next access to the blocks.

Abstract: The present disclosure relates to a method for instruction processing with a processor having multiple execution units. The processor includes a dependency cache containing instructions in association with respective execution unit indicators. The method includes: tracking the number of dependent instructions currently assigned to each execution unit of the processor respectively. In response to receiving an instruction of a dependency chain, the execution unit assigned to a previous instruction of the dependency chain on which depends the received instruction may be identified in the dependency cache. In case more than a predefined maximum number of dependent instructions of at least one dependency chain is currently assigned to the identified execution unit, another execution unit of the processor may be selected for scheduling the received instruction, otherwise the received instruction may be scheduled on the identified execution unit.

Abstract: The present disclosure relates to a method for instruction processing with a processor having multiple execution units. The processor includes a dependency cache containing instructions in association with respective execution unit indicators. The method includes: tracking the number of dependent instructions currently assigned to each execution unit of the processor respectively. In response to receiving an instruction of a dependency chain, the execution unit assigned to a previous instruction of the dependency chain on which depends the received instruction may be identified in the dependency cache. In case more than a predefined maximum number of dependent instructions of at least one dependency chain is currently assigned to the identified execution unit, another execution unit of the processor may be selected for scheduling the received instruction, otherwise the received instruction may be scheduled on the identified execution unit.

Abstract: A unit operates on a sum term and a carry term separated into a high part and a low part of a product and performs a method that includes iteratively computing a carry save product and separating the carry save product into the high part and the low part: an intermediate product. The unit generates an intermediate wide result by performing a wide addition of the intermediate product to generate an unrounded sum for the high part (i.e., a fused-multiply-add high part) and the low part (i.e., a fused-multiply-add high part). The unit pre-aligns the intermediate wide result on two fixed length shifters such that the fused-multiply-add high part and the fused-multiply-add low part are pre-aligned to each fit on one shifter of the two fixed length shifters.

Abstract: A circuit is provided which includes arithmetic computation logic configured to add or subtract operands of variable length to produce a result in a sign-magnitude data format. The circuit also includes an overflow detector to provide an overflow signal indicative of whether the result fits within a specified result length l. The overflow detector operates on the operands prior to the arithmetic computation logic producing the result to determine, independent of the result produced by the arithmetic computation logic, whether the result fits within the specified result length l.

Abstract: A unit operates on a sum term and a carry term separated into a high part and a low part of a product and performs a method that includes iteratively computing a carry save product and separating the carry save product into the high part and the low part: an intermediate product. The unit generates an intermediate wide result by performing a wide addition of the intermediate product to generate an unrounded sum for the high part (i.e., a fused-multiply-add high part) and the low part (i.e., a fused-multiply-add high part). The unit pre-aligns the intermediate wide result on two fixed length shifters such that the fused-multiply-add high part and the fused-multiply-add low part are pre-aligned to each fit on one shifter of the two fixed length shifters.

Abstract: Disclosed herein is a computer implemented method for performing multiply-add operations of binary numbers P, Q, R, S, B in an arithmetic unit of a processor, the operation calculating a result as an accumulated sum, which equals to B+n×P×Q+m×R×S, where n and m are natural numbers. Further disclosed herein is an arithmetic unit configured to implement multiply-add operations of binary numbers P, Q, R, S, B comprising at least a first binary arithmetic unit for calculating an aligned high part result and a second binary arithmetic unit for calculating an aligned low part result of the multiply-add operations.

Abstract: A unit operates on a sum term and a carry term separated into a high part and a low part of a product and performs a method that includes iteratively computing a carry save product and separating the carry save product into the high part and the low part: an intermediate product. The unit generates an intermediate wide result by performing a wide addition of the intermediate product to generate an unrounded sum for the high part (i.e., a fused-multiply-add high part) and the low part (i.e., a fused-multiply-add high part). The unit pre-aligns the intermediate wide result on two fixed length shifters such that the fused-multiply-add high part and the fused-multiply-add low part are pre-aligned to each fit on one shifter of the two fixed length shifters.

Abstract: Disclosed herein is a computer implemented method for performing multiply-add operations of binary numbers P, Q, R, S, B in an arithmetic unit of a processor, the operation calculating a result as an accumulated sum, which equals to B+n×P×Q+m×R×S, where n and m are natural numbers. Further disclosed herein is an arithmetic unit configured to implement multiply-add operations of binary numbers P, Q, R, S, B comprising at least a first binary arithmetic unit for calculating an aligned high part result and a second binary arithmetic unit for calculating an aligned low part result of the multiply-add operations.

Abstract: A method, computer program product and/or system is disclosed. According to an aspect of this invention, a device under test (DUT) is switched to a functional test mode. In some embodiments of the present invention, the DUT receives a general scan design (GSD) pattern while in the functional test mode. In some embodiments, the DUT executes a first functional test corresponding to the GSD pattern. In yet other embodiments, the DUT further comprises a state machine that controls the execution of the first functional test. The DUT may further store the output address, the output data, and the status to an address register, a data register, and a status register, respectively and/or send the output address, the output data, and the status to an address register to an automatic testing equipment (ATE).

Abstract: Disclosed herein is a computer implemented method for performing multiply-add operations of binary numbers P, Q, R, S, B in an arithmetic unit of a processor, the operation calculating a result as an accumulated sum, which equals to B+n×P×Q+m×R×S, where n and m are natural numbers. Further disclosed herein is an arithmetic unit configured to implement multiply-add operations of binary numbers P, Q, R, S, B comprising at least a first binary arithmetic unit for calculating an aligned high part result and a second binary arithmetic unit for calculating an aligned low part result of the multiply-add operations.

Abstract: A processor unit can be used to rapidly search a string of characters. The processor unit can include vector registers each having M vector elements, each vector element having n bits of data for containing an encoded character. An M×M matrix of comparators within the processor unit can be used to compare elements of a first register storing a reference string and elements of a second register storing a target string. A logic gate is associated with each diagonal of the matrix of comparators, and is configured to combine the results of comparators along the diagonal, resulting in a bit vector indicating characters of the target string that fully match the reference string and characters that partially match the reference string. Correction logic within the processor unit can suppress indications of a partial match or of a full match in the bit vector.

Abstract: Embodiments of the invention include a computer-implemented method of processor branch prediction. This method aims at training a machine-learning model of processor branch behavior while a processing unit executes computer instructions. Such instructions include branch instructions, load instructions and store instructions. The load instructions and the store instructions cause a control unit of the processing unit to load data from a memory into processor registers and store data from the processor registers to the memory, respectively. Basically, the training of the model involves, for each of N branch instructions (N>2) encountered whilst the processing unit executes said branch instructions: identifying a next branch instruction; and feeding the machine-learning model with carefully chosen inputs.

Abstract: Embodiments of the invention include a computer-implemented method of processor branch prediction. This method aims at training a machine-learning model of processor branch behavior while a processing unit executes computer instructions. Such instructions include branch instructions, load instructions and store instructions. The load instructions and the store instructions cause a control unit of the processing unit to load data from a memory into processor registers and store data from the processor registers to the memory, respectively. Basically, the training of the model involves, for each of N branch instructions (N>2) encountered whilst the processing unit executes said branch instructions: identifying a next branch instruction; and feeding the machine-learning model with carefully chosen inputs.

Abstract: Aspects include a system having logic built-in self-test (LBIST) circuitry for use in an integrated circuit with scan chains. The system includes a pattern generator configured for generating scan-in test values for said scan chains; a signature register configured for collecting scan-out responses from said scan chains after a clock sequence; an on-product control generator configured for controlling at least one test parameter; one or more microcode array or memory elements configured to receive inputs to initialize fields in the microcode array or memory elements; and a test controller. The test controller includes a reader component configured for reading test parameters from a field of the microcode array or the memory elements; and a programming component configured for configuring the on-product control generator and the pattern generator with a LBIST pattern according to the read test parameters.