Patents by Inventor Ceredig Roberts

Ceredig Roberts has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140231894
    Abstract: A method is disclosed for forming a memory device having buried access lines (e.g., wordlines) and buried data/sense lines (e.g., digitlines) disposed below vertical cell contacts. The buried wordlines may be formed trenches in a substrate extending in a first direction, and the buried digitlines may be formed from trenches in a substrate extending in a second direction perpendicular to the first direction. The buried digitlines may be coupled to a silicon sidewall by a digitline contact disposed between the digitlines and the silicon substrate.
    Type: Application
    Filed: April 30, 2014
    Publication date: August 21, 2014
    Applicant: Micron Technology, Inc.
    Inventors: Kunal Parekh, Ceredig Roberts, Thy Tran, Jim Jozwiak, David Hwang
  • Patent number: 8716116
    Abstract: A method is disclosed for forming a memory device having buried access lines (e.g., wordlines) and buried data/sense lines (e.g., digitlines) disposed below vertical cell contacts. The buried wordlines may be formed trenches in a substrate extending in a first direction, and the buried digitlines may be formed from trenches in a substrate extending in a second direction perpendicular to the first direction. The buried digitlines may be coupled to a silicon sidewall by a digitline contact disposed between the digitlines and the silicon substrate.
    Type: Grant
    Filed: March 10, 2010
    Date of Patent: May 6, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Kunal Parekh, Ceredig Roberts, Thy Tran, Jim Jozwiak, David Hwang
  • Patent number: 8349699
    Abstract: First and second isolation trenches are formed into semiconductive material of a semiconductor substrate. The first isolation trench has a narrowest outermost cross sectional dimension which is less than that of the second isolation trench. An insulative layer is deposited to within the first and second isolation trenches effective to fill remaining volume of the first isolation trench within the semiconductive material but not that of the second isolation trench within the semiconductive material. The insulative layer comprises silicon dioxide deposited from flowing TEOS to the first and second isolation trenches. A spin-on-dielectric is deposited over the silicon dioxide deposited from flowing the TEOS within the second isolation trench within the semiconductive material, but not within the first isolation trench within the semiconductive material. The spin-on-dielectric is deposited effective to fill remaining volume of the second isolation trench within the semiconductive material.
    Type: Grant
    Filed: August 16, 2011
    Date of Patent: January 8, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Robert D. Patraw, Martin Ceredig Roberts, Keith R. Cook
  • Publication number: 20110300689
    Abstract: First and second isolation trenches are formed into semiconductive material of a semiconductor substrate. The first isolation trench has a narrowest outermost cross sectional dimension which is less than that of the second isolation trench. An insulative layer is deposited to within the first and second isolation trenches effective to fill remaining volume of the first isolation trench within the semiconductive material but not that of the second isolation trench within the semiconductive material. The insulative layer comprises silicon dioxide deposited from flowing TEOS to the first and second isolation trenches. A spin-on-dielectric is deposited over the silicon dioxide deposited from flowing the TEOS within the second isolation trench within the semiconductive material, but not within the first isolation trench within the semiconductive material. The spin-on-dielectric is deposited effective to fill remaining volume of the second isolation trench within the semiconductive material.
    Type: Application
    Filed: August 16, 2011
    Publication date: December 8, 2011
    Applicant: Micron Technology, Inc.
    Inventors: Robert D. Patraw, M. Ceredig Roberts, Keith R. Cook
  • Publication number: 20110220994
    Abstract: A method is disclosed for forming a memory device having buried access lines (e.g., wordlines) and buried data/sense lines (e.g., digitlines) disposed below vertical cell contacts. The buried wordlines may be formed trenches in a substrate extending in a first direction, and the buried digitlines may be formed from trenches in a substrate extending in a second direction perpendicular to the first direction. The buried digitlines may be coupled to a silicon sidewall by a digitline contact disposed between the digitlines and the silicon substrate.
    Type: Application
    Filed: March 10, 2010
    Publication date: September 15, 2011
    Applicant: Micron Technology, Inc.
    Inventors: Kunal Parekh, Ceredig Roberts, Thy Tran, Jim Jozwiak, David Hwang
  • Patent number: 8012847
    Abstract: First and second isolation trenches are formed into semiconductive material of a semiconductor substrate. The first isolation trench has a narrowest outermost cross sectional dimension which is less than that of the second isolation trench. An insulative layer is deposited to within the first and second isolation trenches effective to fill remaining volume of the first isolation trench within the semiconductive material but not that of the second isolation trench within the semiconductive material. The insulative layer comprises silicon dioxide deposited from flowing TEOS to the first and second isolation trenches. A spin-on-dielectric is deposited over the silicon dioxide deposited from flowing the TEOS within the second isolation trench within the semiconductive material, but not within the first isolation trench within the semiconductive material. The spin-on-dielectric is deposited effective to fill remaining volume of the second isolation trench within the semiconductive material.
    Type: Grant
    Filed: April 1, 2005
    Date of Patent: September 6, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Robert D. Patraw, M. Ceredig Roberts, Keith R. Cook
  • Patent number: 7935999
    Abstract: A memory device comprises an active area comprising a source and at least two drains defining a first axis. At least two substantially parallel word lines are defined by a first pitch, with one word line located between each drain and the source. Digit lines are defined by a second pitch, one of the digit lines being coupled to the source and forming a second axis. The active areas of the memory array are tilted at 45° to the grid defined by the word lines and digit lines. The word line pitch is about 1.5F, while the digit line pitch is about 3F.
    Type: Grant
    Filed: February 22, 2010
    Date of Patent: May 3, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Gordon A. Haller, David K. Hwang, Sanh Dang Tang, Ceredig Roberts
  • Publication number: 20100148249
    Abstract: A memory device comprises an active area comprising a source and at least two drains defining a first axis. At least two substantially parallel word lines are defined by a first pitch, with one word line located between each drain and the source. Digit lines are defined by a second pitch, one of the digit lines being coupled to the source and forming a second axis. The active areas of the memory array are tilted at 45° to the grid defined by the word lines and digit lines. The word line pitch is about 1.5F, while the digit line pitch is about 3F.
    Type: Application
    Filed: February 22, 2010
    Publication date: June 17, 2010
    Applicant: Micron Technology, Inc.
    Inventors: Gordon A. Haller, David K. Hwang, Sanh Dang Tang, Ceredig Roberts
  • Patent number: 7687342
    Abstract: A memory device comprises an active area comprising a source and at least two drains defining a first axis. At least two substantially parallel word lines are defined by a first pitch, with one word line located between each drain and the source. Digit lines are defined by a second pitch, one of the digit lines being coupled to the source and forming a second axis. The active areas of the memory array are tilted at 45° to the grid defined by the word lines and digit lines. The word line pitch is about 1.5F, while the digit line pitch is about 3F.
    Type: Grant
    Filed: September 1, 2005
    Date of Patent: March 30, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Gordon A. Haller, David K. Hwang, Sanh Dang Tang, Ceredig Roberts
  • Patent number: 7557048
    Abstract: The invention includes methods of forming and/or passivating semiconductor constructions. In particular aspects, various oxides of a semiconductor substrate can be formed by exposing semiconductive material of the substrate to deuterium-enriched steam. In other aspects, a semiconductor construction is passivated by subjecting the construction to an anneal at a temperature of greater than or equal to 350° C. while exposing the construction to a deuterium-enriched ambient.
    Type: Grant
    Filed: June 21, 2006
    Date of Patent: July 7, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Kunal R. Parekh, Chandra V. Mouli, M. Ceredig Roberts, Fernando Gonzalez
  • Patent number: 7488664
    Abstract: A capacitor structure for a semiconductor assembly and a method for forming same are described. The capacitor structure comprises a pair of electrically separated capacitor electrodes and a capacitor electrode being common to only the pair of electrically separated capacitor electrodes.
    Type: Grant
    Filed: August 10, 2005
    Date of Patent: February 10, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Keith Cook, Ceredig Roberts
  • Patent number: 7387940
    Abstract: The invention includes methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating integrated circuitry including memory circuitry, and integrated circuitry such as memory integrated circuitry.
    Type: Grant
    Filed: August 9, 2005
    Date of Patent: June 17, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Robert D. Patraw, M. Ceredig Roberts, Keith R. Cook
  • Patent number: 7368372
    Abstract: The invention includes methods of fabricating multiple sets of field effect transistors. In one implementation, an etch stop layer is formed over an insulative capping layer which is formed over a conductive gate layer formed over a substrate. The etch stop layer, the insulative capping layer, and the conductive gate layer are patterned and etched to form a first set of conductive gate constructions over the substrate. A dielectric material is formed and planarized over the first set of gate constructions. Thereafter, the insulative capping layer and the conductive gate layer are patterned and etched to form a second set of conductive gate constructions over the substrate. Other aspects and implementations are contemplated.
    Type: Grant
    Filed: March 21, 2006
    Date of Patent: May 6, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Fred D. Fishburn, Martin Ceredig Roberts
  • Patent number: 7247919
    Abstract: An integrated circuit which provides a FET device having reduced GIDL current is described. A semiconductor substrate is provided wherein active regions are separated by an isolation region and a gate oxide layer is provided on the active regions. A gate electrode is provided upon the gate oxide layer wherein beneath an edge of the gate electrode, a gate-drain overlap region having a high dose ion implant is provided.
    Type: Grant
    Filed: August 25, 2000
    Date of Patent: July 24, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Chandra V. Mouli, Ceredig Roberts
  • Patent number: 7189662
    Abstract: The invention includes methods of forming and/or passivating semiconductor constructions. In particular aspects, various oxides of a semiconductor substrate can be formed by exposing semiconductive material of the substrate to deuterium-enriched steam. In other aspects, a semiconductor construction is passivated by subjecting the construction to an anneal at a temperature of greater than or equal to 350° C. while exposing the construction to a deuterium-enriched ambient.
    Type: Grant
    Filed: August 24, 2004
    Date of Patent: March 13, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Kunal R. Parekh, Chandra V. Mouli, M. Ceredig Roberts, Fernando Gonzalez
  • Publication number: 20070045712
    Abstract: A memory device comprises an active area comprising a source and at least two drains defining a first axis. At least two substantially parallel word lines are defined by a first pitch, with one word line located between each drain and the source. Digit lines are defined by a second pitch, one of the digit lines being coupled to the source and forming a second axis. The active areas of the memory array are tilted at 45° to the grid defined by the word lines and digit lines. The word line pitch is about 1.5 F, while the digit line pitch is about 3 F.
    Type: Application
    Filed: September 1, 2005
    Publication date: March 1, 2007
    Inventors: Gordon Haller, David Hwang, Sanh Tang, Ceredig Roberts
  • Publication number: 20070034928
    Abstract: A capacitor structure for a semiconductor assembly and a method for forming same are described. The capacitor structure comprises a pair of electrically separated capacitor electrodes and a capacitor electrode being common to only the pair of electrically separated capacitor electrodes.
    Type: Application
    Filed: August 10, 2005
    Publication date: February 15, 2007
    Inventors: Keith Cook, Ceredig Roberts
  • Publication number: 20060263964
    Abstract: A process for the fabrication of an integrated circuit which provides a FET device having reduced GIDL current is described. A semiconductor substrate is provided wherein active regions are separated by an isolation region, and a gate oxide layer is form on the active regions. Gate electrodes are formed upon the gate oxide layer in the active regions. An angled, high dose, ion implant is performed to selectively dope the gate oxide layer beneath an edge of each gate electrode in a gate-drain overlap region, and the fabrication of the integrated circuit is completed.
    Type: Application
    Filed: July 31, 2006
    Publication date: November 23, 2006
    Inventors: Chandra Mouli, Ceredig Roberts
  • Patent number: 7105881
    Abstract: The invention includes a DRAM device. The device has an access transistor construction, and the access transistor construction has a pair of source/drain regions. A halo region is associated with one of the source/drain regions of the access transistor construction and no comparable halo region is associated with the other of the source/drain regions of the access transistor construction. The invention also encompasses methods of forming DRAM devices.
    Type: Grant
    Filed: December 19, 2002
    Date of Patent: September 12, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Martin Ceredig Roberts
  • Patent number: 7071058
    Abstract: Capacitors, DRAM circuitry, and methods of forming the same are described. In one embodiment, a capacitor comprises a first container which is joined with a substrate node location and has an opening defining a first interior area. A second container is joined with the node location and has an opening defining a second interior area. The areas are spaced apart from one another in a non-overlapping relationship. A dielectric layer and a conductive capacitor electrode layer are disposed operably proximate the first and second containers. In another embodiment, the first and second containers are generally elongate and extend away from the node location along respective first and second central axes. The axes are different and spaced apart from one another. In yet another embodiment, a conductive layer of material is disposed over and in electrical communication with a substrate node location. The layer of material has an outer surface with a first region and a second region spaced apart from the first region.
    Type: Grant
    Filed: April 2, 2004
    Date of Patent: July 4, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Martin Ceredig Roberts, Christophe Pierrat