Patents by Inventor Cha Dong

Cha Dong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120052438
    Abstract: A photoresist composition and method of forming pattern using the same are provided. The photoresist composition contains an alkali-soluble novolac resin, a photosensitizer including a compound of Chemical Formula 1, and a solvent.
    Type: Application
    Filed: May 26, 2011
    Publication date: March 1, 2012
    Inventors: Cha-Dong KIM, Sang-Hyun Yun, Jung-In Park, Hi-Kuk Lee, Deok-Man Kang, Youn-Suk Kim, Sae-Tae Oh
  • Publication number: 20110287360
    Abstract: A photoresist composition is provided. The photoresist composition includes an alkali-soluble resin; a photosensitizer containing a first compound that contains a diazonaphthoquinone represented by Formula 1 and a second compound that contains a diazonaphthoquinone represented by Formula 2; and a solvent. and R1 is selected from the group consisting of a hydrogen atom, an alkyl group having 1 to 4 carbons, an alkenyl group having 2 to 4 carbons, a cycloalkyl group having 3 to 8 carbons, and an aryl group having 6 to 12 carbons, and R2 is selected from the group consisting of Cl, F, Br, and I.
    Type: Application
    Filed: February 28, 2011
    Publication date: November 24, 2011
    Applicants: AZ ELECTRONIC MATERIALS K.K., SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hi-Kuk LEE, Sang-Hyun YUN, Cha-Dong KIM, Jung-In PARK, Deok-Man KANG, Youn-Suk KIM, Sae-Tae OH
  • Publication number: 20110236825
    Abstract: In a photoresist composition suitable for forming a photoresist pattern having a high profile angle, and a method of forming a photoresist pattern using the same, the photoresist composition includes an alkali-soluble resin, a quinone diazide containing compound, a compound represented by Formula 1, and a solvent: wherein R1, R2 and R3 are independently H, C1-4 alkyl, C2-4 alkenyl, C3-8 cycloalkyl, or C6-12 aryl.
    Type: Application
    Filed: January 20, 2011
    Publication date: September 29, 2011
    Inventors: Jung-In PARK, Hi-Kuk Lee, Sang-Hyun Yun, Cha-Dong Kim, Shi-Jin Sung, Sung-Yeol Jin, Sang-Tae Kim, Yong-Il Kim, Eun-Sang Lee
  • Publication number: 20110230019
    Abstract: An approach for patterning and etching without a mask is provided in a manufacturing a thin-film transistor, a gate electrode, a gate insulating layer, a semiconductor layer, an ohmic contact layer and source metal layer of a substrate. A first photoresist pattern including a first photo pattern and a second photo pattern is formed using a digital exposure device by generating a plurality of spot beams, the first photo pattern is formed to a first region of the base substrate and has a first thickness, and the second photo pattern is formed to a second region adjacent to the first region, and has a second thickness and a width in a range of about 50% to about 60% of a diameter of the spot beam. The source metal layer is patterned to form a source electrode and a drain electrode, and the source electrode and the drain electrode are spaced apart from each other in the first region of an active pattern.
    Type: Application
    Filed: October 8, 2010
    Publication date: September 22, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Hyun YUN, Cha-Dong KIM, Jung-In PARK, Hi-Kuk LEE
  • Publication number: 20110205508
    Abstract: A digital exposure method and a digital exposure device for performing the method are disclosed. In the method, a graphic data system file is produced in correspondence with each of a plurality of patterns formed on a substrate. Then, a digital micromirror device on/off data is generated from the graphic data system file. Then, the substrate is exposed in response to the digital micromirror device on/off data. Thus, at least a first exposure for forming a first pattern of a display panel, and a second exposure for forming identification numbers of a substrate and each display panel and removing an edge portion of the substrate may be simultaneously performed, to simplify the exposure process decrease costs.
    Type: Application
    Filed: October 18, 2010
    Publication date: August 25, 2011
    Inventors: Sang-Hyun Yun, Hi-Kuk Lee, Sang-Woo Bae, Cha-Dong Kim, Jung-In Park
  • Publication number: 20110199620
    Abstract: An apparatus and a method for determining an overlap distance of an optical head is disclosed. Positions and light amount distributions of each light spot can be measured, which may be provided from an optical head to a substrate. Gaussian distribution may be applied to the positions and the light amount distributions to calculate a compensation model of each of the light spots. A first accumulated light amount corresponding to each first area of the substrate may be calculated if the optical head is scanning along a first direction of the substrate using the compensation model. A second accumulated light amount corresponding to each second area overlapped with the each first area is calculated if the optical head is scanning along the first direction, which is moved in a second direction by a first distance using the compensation model. An overlap distance may be determined based on a uniformity of summations of the first and second accumulated light amount.
    Type: Application
    Filed: October 12, 2010
    Publication date: August 18, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Hyun YUN, Hi-Kuk LEE, Sang-Woo BAE, Cha-Dong KIM, Jung-In PARK
  • Patent number: 7927932
    Abstract: A semiconductor device according to example embodiments may have a plurality of stacked transistors. The semiconductor device may have a lower insulating layer formed on a semiconductor substrate and an upper channel body pattern formed on the lower insulating layer. A source region and a drain region may be formed within the upper channel body pattern, and a non-metal transfer gate electrode may be disposed on the upper channel body pattern between the source and drain regions. The non-metal transfer gate electrode, the upper channel body pattern, and the lower insulating layer may be covered by an intermediate insulating layer. A metal word line may be disposed within the intermediate insulating layer to contact at least an upper surface of the non-metal transfer gate electrode. An insulating spacer may be disposed on a sidewall of the metal word line.
    Type: Grant
    Filed: September 23, 2010
    Date of Patent: April 19, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Han-Byung Park, Soon-Moon Jung, Hoon Lim, Cha-Dong Yeo, Byoung-Keun Son, Jae-Joo Shim, Chang-Min Hong
  • Publication number: 20110014754
    Abstract: A semiconductor device according to example embodiments may have a plurality of stacked transistors. The semiconductor device may have a lower insulating layer formed on a semiconductor substrate and an upper channel body pattern formed on the lower insulating layer. A source region and a drain region may be formed within the upper channel body pattern, and a non-metal transfer gate electrode may be disposed on the upper channel body pattern between the source and drain regions. The non-metal transfer gate electrode, the upper channel body pattern, and the lower insulating layer may be covered by an intermediate insulating layer. A metal word line may be disposed within the intermediate insulating layer to contact at least an upper surface of the non-metal transfer gate electrode. An insulating spacer may be disposed on a sidewall of the metal word line.
    Type: Application
    Filed: September 23, 2010
    Publication date: January 20, 2011
    Inventors: Han-Byung Park, Soon-Moon Jung, Hoon Lim, Cha-Dong Yeo, Byoung-Keun Son, Jae-Joo Shim, Chang-Min Hong
  • Patent number: 7825472
    Abstract: A semiconductor device according to example embodiments may have a plurality of stacked transistors. The semiconductor device may have a lower insulating layer formed on a semiconductor substrate and an upper channel body pattern formed on the lower insulating layer. A source region and a drain region may be formed within the upper channel body pattern, and a non-metal transfer gate electrode may be disposed on the upper channel body pattern between the source and drain regions. The non-metal transfer gate electrode, the upper channel body pattern, and the lower insulating layer may be covered by an intermediate insulating layer. A metal word line may be disposed within the intermediate insulating layer to contact at least an upper surface of the non-metal transfer gate electrode. An insulating spacer may be disposed on a sidewall of the metal word line.
    Type: Grant
    Filed: July 18, 2008
    Date of Patent: November 2, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Han-Byung Park, Soon-Moon Jung, Hoon Lim, Cha-Dong Yeo, Byoung-Keun Son, Jae-Joo Shim, Chang-Min Hong
  • Publication number: 20090020817
    Abstract: A semiconductor device according to example embodiments may have a plurality of stacked transistors. The semiconductor device may have a lower insulating layer formed on a semiconductor substrate and an upper channel body pattern formed on the lower insulating layer. A source region and a drain region may be formed within the upper channel body pattern, and a non-metal transfer gate electrode may be disposed on the upper channel body pattern between the source and drain regions. The non-metal transfer gate electrode, the upper channel body pattern, and the lower insulating layer may be covered by an intermediate insulating layer. A metal word line may be disposed within the intermediate insulating layer to contact at least an upper surface of the non-metal transfer gate electrode. An insulating spacer may be disposed on a sidewall of the metal word line.
    Type: Application
    Filed: July 18, 2008
    Publication date: January 22, 2009
    Inventors: Han-Byung Park, Soon-Moon Jung, Hoon Lim, Cha-Dong Yeo, Byoung-Keun Son, Jae-Joo Shim, Chang-Min Hong
  • Publication number: 20070117316
    Abstract: A semiconductor device and a method of manufacturing the same, wherein first and second gate electrodes are formed to have a spacer shape. The length of an underlying dielectric film can be automatically controlled. A gate oxide film and a third gate electrode are formed between the first and second gate electrodes. Voids are not generated when burying the third conductive film. A thickness and width of the gate oxide film can be freely controlled.
    Type: Application
    Filed: June 16, 2006
    Publication date: May 24, 2007
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Cha Dong, Seung Shin
  • Publication number: 20070099434
    Abstract: An oxide film is formed by a radical oxidization process and nitrogen is introduced into the oxide film by an annealing process using NO gas. The nitrogen gathered at the interface of the oxide film and a semiconductor substrate is re-distributed by an annealing process using a mixed gas including O2 and N2.
    Type: Application
    Filed: June 30, 2006
    Publication date: May 3, 2007
    Applicant: Hynix Semiconductor Inc.
    Inventor: Cha Dong
  • Patent number: 7141116
    Abstract: Provided are improved methods for forming silicon films, particularly single-crystal silicon films from amorphous silicon films in which a single-crystal silicon substrate is prepared by removing any native oxide, typically using an aqueous HF solution, and placed in a reaction chamber. The substrate is then heated from about 350° C. to a first deposition temperature under a first ambient to induce single-crystal epitaxial silicon deposition primarily on exposed silicon surfaces. The substrate is then heated to a second deposition temperature under a second ambient that will maintain the single-crystal epitaxial silicon deposition on exposed single-crystal silicon while inducing amorphous epitaxial silicon deposition on insulating surfaces. The amorphous epitaxial silicon can then be converted to single-crystal silicon using a solid phase epitaxy process to form a thin, high quality silicon layer.
    Type: Grant
    Filed: April 1, 2005
    Date of Patent: November 28, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong Hoon Son, Jae Young Park, Cha Dong Yeo, Jong Wook Lee, Yu Gyun Shin
  • Publication number: 20060194389
    Abstract: A method is provided for fabricating a flash memory device, preventing particles from spreading around edges of a wafer while pre-cleaning a tunnel oxide film by removing particles at the edges of the wafer. Accordingly, it is able to overcome the problems arising from quality deterioration of the tunnel oxide film and defective patterns.
    Type: Application
    Filed: December 2, 2005
    Publication date: August 31, 2006
    Applicant: Hynix Semiconductor Inc.
    Inventors: Cha Dong, Jae Kwon
  • Patent number: 7074683
    Abstract: A semiconductor device comprises a device isolation layer disposed in a portion of a substrate of first conductivity type. An outline of the device isolation layer defines an active region of the substrate. An impurity diffused region of second conductivity type may be formed in a portion of the active region; and a silicide layer may be formed to cover the impurity diffused region of second conductivity type. The device isolation layer may include a recess formed therein to expose a portion of the substrate of first conductivity type adjacent to the impurity diffused region of second conductivity type. The silicide layer that is formed to cover the impurity diffused layer of second conductivity type may extend over and against the exposed region of the substrate of first conductivity type that was exposed by the recess of the device isolation layer.
    Type: Grant
    Filed: March 8, 2004
    Date of Patent: July 11, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sun-Ha Hwang, Young-Ok Kim, Cha-Dong Yeo
  • Publication number: 20060141711
    Abstract: The present invention relates to a method of manufacturing flash memory devices. According to the present invention, an inter-gate insulating film formed between a floating gate and a control gate is formed to have an NONON structure, thus removing the interface of polysilicon and an oxide film. It is thus possible to prevent a thickness of an inter-gate insulating film from increasing due to a subsequent oxidization process. Furthermore, the thickness of the inter-gate insulating film can be kept uniform regardless of the shape of a cell. It is thus possible to make uniform the operating speed among cells and also to reduce the slow program fail rate.
    Type: Application
    Filed: May 17, 2005
    Publication date: June 29, 2006
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventor: Cha Dong
  • Publication number: 20060057806
    Abstract: Provided is a method for manufacturing a flash memory device, in which an oxidation process is carried out on the disclosed top surface of a semiconductor substrate to form a surface oxide film in the form of bird's beak with an appropriate width before conducting an etching process for trench. Thus, the present invention prevents the effect of thinning tunnel oxide film while reducing a critical dimension of an active region. And, it is possible to assure a normal cell operation by the Fowler-Nordheim (FN) tunneling effect owing to preventing the thinning tunnel oxide film.
    Type: Application
    Filed: June 6, 2005
    Publication date: March 16, 2006
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventor: Cha Dong
  • Publication number: 20050161729
    Abstract: The present invention relates to a flash memory cell and method of manufacturing the same. The flash memory cell comprises a trench for defining a semiconductor substrate to be an active region and an inactive region, a trench insulating film burying the trench and having a given protrusion, an impurity region formed in the active region, a floating gate isolated by the protrusion and having rugged portions, and a dielectric film and a control gate formed on the floating gate. Therefore, the present invention can significantly simplify the process, improve the yield of a product and reduce the manufacturing cost.
    Type: Application
    Filed: March 15, 2005
    Publication date: July 28, 2005
    Inventors: Cha Dong, Kwang Joo
  • Publication number: 20050130433
    Abstract: The present invention relates to a method for forming an isolation film in a semiconductor device. After a trench for isolation is formed, a polymer film is stripped by a post cleaning process using BFN. A pre-treatment cleaning process using only SC-1 is performed and a sidewall oxidization process is then carried out. It is therefore possible to improve fail of the roughness of the trench sidewall and to easily strip polymer. Furthermore, since a conventional PET process is omitted, an isolation film manufacturing process is simplified. It is also possible to prohibit out-diffusion of dopants injected into a semiconductor substrate through a pre-treatment cleaning process using CLN N before the sidewall oxidization process. Incidentally, by forming a slope at the top corner of the trench, it is possible to prevent a gate oxide film thinning phenomenon that the gate oxide film thinner than a desired thickness is deposited at the trench corner.
    Type: Application
    Filed: June 24, 2004
    Publication date: June 16, 2005
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Cha Dong, Il Han
  • Publication number: 20050095778
    Abstract: Disclosed is a method for manufacturing a capacitor of a semiconductor device. The method includes the steps of providing a substrate having a storage node plug, forming a PE-TEOS layer and a hard mask exposing a storage node contact area on the substrate, forming a storage node contact having a side profile of a positive and negative pattern through etching the PE-TEOS layer, removing the hard mask by etching-back the hard mask, performing an annealing process with respect to a resultant structure, forming a silicon layer on the silicon substrate, which passes through the annealing process, coating a photoresist film on an entire surface of the substrate, forming a storage node electrode by etching-back the photoresist film and the silicon layer, removing a remaining photoresist film, and forming a dielectric layer and a silicon layer on a storage node electrode structure.
    Type: Application
    Filed: July 9, 2004
    Publication date: May 5, 2005
    Inventors: Cha Dong, Il Han