Patents by Inventor Cha-Jea Jo
Cha-Jea Jo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230238417Abstract: An image sensor package includes an image sensor chip on a package substrate, a logic chip on the package substrate and perpendicularly overlapping the image sensor chip, and a memory chip on the package substrate and perpendicularly overlapping the image sensor chip and logic chip. The logic chip processes a pixel signal output from the image sensor chip. The memory chip is electrically connected to the image sensor chip through a conductive wire and stores at least one of the pixel signal from the image sensor chip or a pixel signal processed by the logic chip. The memory chip receives the pixel signal output from the image sensor chip through the conductive wire and receives the pixel signal processed by the logic chip through the image sensor chip and the conductive wire.Type: ApplicationFiled: March 28, 2023Publication date: July 27, 2023Inventors: Ji-hwang KIM, Jong-bo SHIM, Sang-uk HAN, Cha-jea JO, Won-il LEE
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Patent number: 11637140Abstract: An image sensor package includes an image sensor chip on a package substrate, a logic chip on the package substrate and perpendicularly overlapping the image sensor chip, and a memory chip on the package substrate and perpendicularly overlapping the image sensor chip and logic chip. The logic chip processes a pixel signal output from the image sensor chip. The memory chip is electrically connected to the image sensor chip through a conductive wire and stores at least one of the pixel signal from the image sensor chip or a pixel signal processed by the logic chip. The memory chip receives the pixel signal output from the image sensor chip through the conductive wire and receives the pixel signal processed by the logic chip through the image sensor chip and the conductive wire.Type: GrantFiled: March 16, 2021Date of Patent: April 25, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-hwang Kim, Jong-bo Shim, Sang-uk Han, Cha-jea Jo, Won-il Lee
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Patent number: 11610865Abstract: A semiconductor package includes a first semiconductor chip in which a through-electrode is provided, a second semiconductor chip connected to a top surface of the first semiconductor chip, a first connection bump attached to a bottom surface of the first semiconductor chip and including a first pillar structure and a first solder layer, and a second connection bump located between the first semiconductor chip and the second semiconductor chip, configured to electrically connect the first semiconductor chip and the second semiconductor chip, and including a second pillar structure and a second solder layer.Type: GrantFiled: March 26, 2021Date of Patent: March 21, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Sun-kyoung Seo, Cha-jea Jo, Soo-hyun Ha
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Patent number: 11244936Abstract: A semiconductor device package and a semiconductor apparatus are provided. The semiconductor device includes a first semiconductor package, a second semiconductor package, and an interposer between the first and second semiconductor packages. The first semiconductor package includes a first semiconductor package substrate and a first semiconductor chip. The second semiconductor package includes a second semiconductor package substrate and a second semiconductor chip. The interposer electrically connects the first semiconductor package to the second semiconductor package and includes a first interposer hole passing through the interposer. The first semiconductor chip includes a second portion which protrudes from a first portion, and the second portion is inserted into the first interposer hole.Type: GrantFiled: June 12, 2019Date of Patent: February 8, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yun Hyeok Im, Hee Seok Lee, Taek Kyun Shin, Cha Jea Jo
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Publication number: 20210217735Abstract: A semiconductor package includes a first semiconductor chip in which a through-electrode is provided, a second semiconductor chip connected to a top surface of the first semiconductor chip, a first connection bump attached to a bottom surface of the first semiconductor chip and including a first pillar structure and a first solder layer, and a second connection bump located between the first semiconductor chip and the second semiconductor chip, configured to electrically connect the first semiconductor chip and the second semiconductor chip, and including a second pillar structure and a second solder layer.Type: ApplicationFiled: March 26, 2021Publication date: July 15, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Sun-kyoung SEO, Cha-jea JO, Soo-hyun HA
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Publication number: 20210202563Abstract: An image sensor package includes an image sensor chip on a package substrate, a logic chip on the package substrate and perpendicularly overlapping the image sensor chip, and a memory chip on the package substrate and perpendicularly overlapping the image sensor chip and logic chip. The logic chip processes a pixel signal output from the image sensor chip. The memory chip is electrically connected to the image sensor chip through a conductive wire and stores at least one of the pixel signal from the image sensor chip or a pixel signal processed by the logic chip. The memory chip receives the pixel signal output from the image sensor chip through the conductive wire and receives the pixel signal processed by the logic chip through the image sensor chip and the conductive wire.Type: ApplicationFiled: March 16, 2021Publication date: July 1, 2021Inventors: Ji-hwang KIM, Jong-bo SHIM, Sang-uk HAN, Cha-jea JO, Won-il LEE
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Patent number: 11018026Abstract: A semiconductor package includes: a plurality of unit redistribution layers vertically stacked, each including: a first polymer layer having a first via hole pattern; a second polymer layer formed on the first polymer layer, and having a redistribution pattern on the first polymer layer and a second via hole pattern in the first via hole pattern; a seed layer covering sidewalls and bottom surfaces of the redistribution pattern and the second via hole pattern; a conductive via plug formed in the second via hole pattern; and a conductive redistribution line formed in the redistribution pattern; a connection terminal disposed on a bottom surface of a lowermost unit redistribution layer and electrically connected to the conductive via plug; a semiconductor device mounted on the unit redistribution layers with a conductive terminal interposed therebetween. Upper surfaces of the second polymer layer, the conductive redistribution line and the conductive via plug are substantially coplanar.Type: GrantFiled: November 29, 2019Date of Patent: May 25, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Un-Byoung Kang, Tae-Je Cho, Hyuek-Jae Lee, Cha-Jea Jo
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Patent number: 10991677Abstract: A semiconductor package includes: a first semiconductor chip in which a through-electrode is provided; a second semiconductor chip connected to a top surface of the first semiconductor chip; a first connection bump attached to a bottom surface of the first semiconductor chip and including a first pillar structure and a first solder layer, and a second connection hump located between the first semiconductor chip and the second semiconductor chip, configured to electrically connect the first semiconductor chip and the second semiconductor chip, and including a second pillar structure and a second solder layer.Type: GrantFiled: April 14, 2020Date of Patent: April 27, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Sun-kyoung Seo, Cha-jea Jo, Soo-hyun Ha
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Patent number: 10971535Abstract: An image sensor package includes an image sensor chip on a package substrate, a logic chip on the package substrate and perpendicularly overlapping the image sensor chip, and a memory chip on the package substrate and perpendicularly overlapping the image sensor chip and logic chip. The logic chip processes a pixel signal output from the image sensor chip. The memory chip is electrically connected to the image sensor chip through a conductive wire and stores at least one of the pixel signal from the image sensor chip or a pixel signal processed by the logic chip. The memory chip receives the pixel signal output from the image sensor chip through the conductive wire and receives the pixel signal processed by the logic chip through the image sensor chip and the conductive wire.Type: GrantFiled: June 29, 2017Date of Patent: April 6, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-hwang Kim, Jong-bo Shim, Sang-uk Han, Cha-jea Jo, Won-il Lee
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Patent number: 10867970Abstract: A semiconductor package includes a first semiconductor chip in which a through-electrode is provided, a second semiconductor chip connected to a top surface of the first semiconductor chip, a first connection bump attached to a bottom surface of the first semiconductor chip and including a first pillar structure and a first solder layer, and a second connection bump located between the first semiconductor chip and the second semiconductor chip, configured to electrically connect the first semiconductor chip and the second semiconductor chip, and including a second pillar structure and a second solder layer.Type: GrantFiled: May 22, 2020Date of Patent: December 15, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Sun-kyoung Seo, Cha-jea Jo, Soo-hyun Ha
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Publication number: 20200286862Abstract: A semiconductor package includes a first semiconductor chip in which a through-electrode is provided, a second semiconductor chip connected to a top surface of the first semiconductor chip, a first connection bump attached to a bottom surface of the first semiconductor chip and including a first pillar structure and a first solder layer, and a second connection bump located between the first semiconductor chip and the second semiconductor chip, configured to electrically connect the first semiconductor chip and the second semiconductor chip, and including a second pillar structure and a second solder layer.Type: ApplicationFiled: May 22, 2020Publication date: September 10, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Sun-kyoung SEO, Cha-jea JO, Soo-hyun HA
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Patent number: 10750112Abstract: A substrate structure for an image sensor module includes a module substrate including a sensor mounting hole, a reinforcing plate on a lower surface of the module substrate, an image sensor chip on the reinforcing plate within the sensor mounting hole, and a reinforcing pattern in the module substrate. The reinforcing plate covers the sensor mounting hole. An upper surface of the image sensor chip may be exposed by the module substrate. The reinforcing pattern is adjacent to the sensor mounting hole and extends in at least one direction.Type: GrantFiled: September 12, 2018Date of Patent: August 18, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-Hwang Kim, Hyo-Eun Kim, Jong-Bo Shim, Cha-Jea Jo, Sang-Uk Han
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Publication number: 20200243488Abstract: A semiconductor package includes: a first semiconductor chip in which a through-electrode is provided; a second semiconductor chip connected to a top surface of the first semiconductor chip; a first connection bump attached to a bottom surface of the first semiconductor chip and including a first pillar structure and a first solder layer, and a second connection hump located between the first semiconductor chip and the second semiconductor chip, configured to electrically connect the first semiconductor chip and the second semiconductor chip, and including a second pillar structure and a second solder layer.Type: ApplicationFiled: April 14, 2020Publication date: July 30, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Sun-kyoung SEO, Cha-jea JO, Soo-hyun HA
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Patent number: 10680025Abstract: A semiconductor package includes a package substrate, an image sensor disposed on the package substrate, and a bonding layer disposed between the package substrate and the image sensor, and including a first region and a second region, the second region has a modulus of elasticity lower than that of the first region and is disposed on a periphery of the first region.Type: GrantFiled: April 13, 2018Date of Patent: June 9, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jong Bo Shim, Cha Jea Jo, Sang Uk Han
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Patent number: 10658341Abstract: A semiconductor package includes: a first semiconductor chip in which a through-electrode is provided; a second semiconductor chip connected to a top surface of the first semiconductor chip; a first connection bump attached to a bottom surface of the first semiconductor chip and including a first pillar structure and a first solder layer, and a second connection hump located between the first semiconductor chip and the second semiconductor chip, configured to electrically connect the first semiconductor chip and the second semiconductor chip, and including a second pillar structure and a second solder layer.Type: GrantFiled: June 21, 2019Date of Patent: May 19, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Sun-kyoung Seo, Cha-jea Jo, Soo-hyun Ha
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Publication number: 20200144076Abstract: A method of fabricating an interposer includes: providing a carrier substrate; forming a unit redistribution layer on the carrier substrate, the unit redistribution layer including a conductive via plug and a conductive redistribution line; and removing the carrier substrate from the unit redistribution layer. The formation of the unit redistribution layer includes: forming a first photosensitive pattern layer including a first via hole pattern; forming a second photosensitive pattern layer including a second via hole pattern and a redistribution pattern on the first photosensitive pattern layer; at least partially filling insides of the first via hole pattern, the second via hole pattern, and the redistribution pattern with a conductive material; and performing planarization to make a top surface of the unit redistribution layer flat.Type: ApplicationFiled: November 29, 2019Publication date: May 7, 2020Inventors: UN-BYOUNG KANG, Tae-Je CHO, Hyuek-Jae LEE, Cha-Jea JO
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Patent number: 10535534Abstract: A method of fabricating an interposer includes: providing a carrier substrate; forming a unit redistribution layer on the carrier substrate, the unit redistribution layer including a conductive via plug and a conductive redistribution line; and removing the carrier substrate from the unit redistribution layer. The formation of the unit redistribution layer includes: forming a first photosensitive pattern layer including a first via hole pattern; forming a second photosensitive pattern layer including a second via hole pattern and a redistribution pattern on the first photosensitive pattern layer; at least partially filling insides of the first via hole pattern, the second via hole pattern, and the redistribution pattern with a conductive material; and performing planarization to make a top surface of the unit redistribution layer flat.Type: GrantFiled: May 4, 2017Date of Patent: January 14, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Un-Byoung Kang, Tae-Je Cho, Hyuek-Jae Lee, Cha-Jea Jo
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Patent number: 10483150Abstract: An apparatus for stacking semiconductor chips includes a push member configured to apply pressure to a semiconductor chip disposed on a substrate. The push member includes a push plate configured to contact the semiconductor chip, and a push rod connected to the push plate. The push plate includes a central portion having an area smaller than an area of an upper side of the semiconductor chip, and a plurality of protrusions disposed at respective ends of the central portion.Type: GrantFiled: November 11, 2016Date of Patent: November 19, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Gun-Ah Lee, Ji-Hwan Hwang, Cha-Jea Jo, Dong-Han Kim, Seung-Kon Mok
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Publication number: 20190312013Abstract: A semiconductor package includes: a first semiconductor chip in which a through-electrode is provided; a second semiconductor chip connected to a top surface of the first semiconductor chip; a first connection bump attached to a bottom surface of the first semiconductor chip and including a first pillar structure and a first solder layer, and a second connection hump located between the first semiconductor chip and the second semiconductor chip, configured to electrically connect the first semiconductor chip and the second semiconductor chip, and including a second pillar structure and a second solder layer.Type: ApplicationFiled: June 21, 2019Publication date: October 10, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Sun-kyoung SEO, Cha-jea JO, Soo-hyun HA
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Publication number: 20190295998Abstract: A semiconductor device package and a semiconductor apparatus are provided. The semiconductor device includes a first semiconductor package, a second semiconductor package, and an interposer between the first and second semiconductor packages. The first semiconductor package includes a first semiconductor package substrate and a first semiconductor chip. The second semiconductor package includes a second semiconductor package substrate and a second semiconductor chip. The interposer electrically connects the first semiconductor package to the second semiconductor package and includes a first interposer hole passing through the interposer. The first semiconductor chip includes a second portion which protrudes from a first portion, and the second portion is inserted into the first interposer hole.Type: ApplicationFiled: June 12, 2019Publication date: September 26, 2019Inventors: Yun Hyeok IM, Hee Seok LEE, Taek Kyun SHIN, Cha Jea JO