Patents by Inventor Cha-Jea Jo
Cha-Jea Jo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8723315Abstract: A flip chip package may include a substrate, a semiconductor chip, main bump structures and auxiliary bump structures. The substrate has a circuit pattern. The semiconductor chip is arranged over the substrate. The semiconductor chip includes a body having semiconductor structures, main pads electrically connected to the semiconductor structures to mainly control the semiconductor structures, and auxiliary pads electrically connected to the semiconductor structures to provide auxiliary control of the semiconductor structures. The main bump structures are interposed between the semiconductor chip and the substrate to electrically connect the circuit pattern with the main pads. The auxiliary bump structures can be interposed between the semiconductor chip and the substrate to electrically connect the circuit pattern with the auxiliary pads.Type: GrantFiled: May 14, 2012Date of Patent: May 13, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Joo Lee, Tae-Joo Hwang, Cha-Jea Jo
-
Publication number: 20130299969Abstract: A semiconductor package includes a first semiconductor chip, a second semiconductor chip and a sealing member. The first semiconductor chip includes a substrate having a first surface and a second surface opposite to the first surface and having an opening that extends in a predetermined depth from the second surface, and a plurality of through electrodes extending in a thickness direction from the first surface, end portions of the through electrodes being exposed through a bottom surface of the opening. The second semiconductor chip is received in the opening and mounted on the bottom surface of the opening. The sealing member covers the second semiconductor chip in the opening.Type: ApplicationFiled: March 15, 2013Publication date: November 14, 2013Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang-Won KIM, Kwang-Chul CHOI, Hyun-Jung SONG, Cha-Jea JO, Eun-Kyoung CHOI, Ji-Seok HONG
-
Publication number: 20120223427Abstract: A flip chip package may include a substrate, a semiconductor chip, main bump structures and auxiliary bump structures. The substrate has a circuit pattern. The semiconductor chip is arranged over the substrate. The semiconductor chip includes a body having semiconductor structures, main pads electrically connected to the semiconductor structures to mainly control the semiconductor structures, and auxiliary pads electrically connected to the semiconductor structures to provide auxiliary control of the semiconductor structures. The main bump structures are interposed between the semiconductor chip and the substrate to electrically connect the circuit pattern with the main pads. The auxiliary bump structures can be interposed between the semiconductor chip and the substrate to electrically connect the circuit pattern with the auxiliary pads.Type: ApplicationFiled: May 14, 2012Publication date: September 6, 2012Inventors: Jong-Joo LEE, Tae-Joo HWANG, Cha-Jea JO
-
Patent number: 8178969Abstract: A flip chip package may include a substrate, a semiconductor chip, main bump structures and auxiliary bump structures. The substrate has a circuit pattern. The semiconductor chip is arranged over the substrate. The semiconductor chip includes a body having semiconductor structures, main pads electrically connected to the semiconductor structures to mainly control the semiconductor structures, and auxiliary pads electrically connected to the semiconductor structures to provide auxiliary control of the semiconductor structures. The main bump structures are interposed between the semiconductor chip and the substrate to electrically connect the circuit pattern with the main pads. The auxiliary bump structures can be interposed between the semiconductor chip and the substrate to electrically connect the circuit pattern with the auxiliary pads.Type: GrantFiled: March 11, 2009Date of Patent: May 15, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Joo Lee, Tae-Joo Hwang, Cha-Jea Jo
-
Patent number: 8088648Abstract: A chip stack package includes a substrate, a plurality of chips, a plurality of adhesive layers and a plug. The substrate has a wiring pattern and a seed layer formed on the wiring pattern. Each of the chips has an electrode pad and a first through-hole that penetrates the electrode pad. The chips are stacked such that the first through-holes are aligned on the seed layer of the substrate. The adhesive layers are interposed between the substrate and one of the chips, as well as between the chips. Each of the adhesive layers has a second through-hole connected to the first through-hole. The plug fills up the first through-holes and the second through-holes and electrically connects the electrode pads to the wiring pattern of the substrate. A cross-sectional area of the plug in the second through-holes may be larger than that of the plug in the first through-holes.Type: GrantFiled: July 21, 2010Date of Patent: January 3, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Cha-Jea Jo, Myung-Kee Chung, Nam-Seog Kim, In-Young Lee, Seok-Ho Kim, Ho-Jin Lee, Ju-Il Choi, Chang-Woo Shin
-
Publication number: 20100285635Abstract: A chip stack package includes a substrate, a plurality of chips, a plurality of adhesive layers and a plug. The substrate has a wiring pattern and a seed layer formed on the wiring pattern. Each of the chips has an electrode pad and a first through-hole that penetrates the electrode pad. The chips are stacked such that the first through-holes are aligned on the seed layer of the substrate. The adhesive layers are interposed between the substrate and one of the chips, as well as between the chips. Each of the adhesive layers has a second through-hole connected to the first through-hole. The plug fills up the first through-holes and the second through-holes and electrically connects the electrode pads to the wiring pattern of the substrate. A cross-sectional area of the plug in the second through-holes may be larger than that of the plug in the first through-holes.Type: ApplicationFiled: July 21, 2010Publication date: November 11, 2010Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Cha-Jea Jo, Myung-Kee Chung, Nam-Seog Kim, In-Young Lee, Seok-Ho Kim, Ho-Jin Lee, Ju-Il Choi, Chang-Woo Shin
-
Patent number: 7638365Abstract: Provided is a stacked chip package and a method for forming the same. A spacer is formed on a side of an upper chip. A conductive line is formed on the spacer to electrically connect upper and lower chips. The reliability of the stacked chip package is improved because wire bonding is not used to electrically connect the upper and lower chips. Further, the overall size of the stacked chip package can be reduced as the height of bonding wire loops does not contribute to the overall stacked chip package height.Type: GrantFiled: January 15, 2007Date of Patent: December 29, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Se-Young Jeong, Nam-Seog Kim, Cha-Jea Jo, Jong-Ho Lee, Myeong-Soon Park
-
Patent number: 7626260Abstract: Provided is a semiconductor device having a cooling path on its bottom surface. The stack-type semiconductor device having a cooling path comprises a stack-type semiconductor chip comprising a first semiconductor chip and a second semiconductor chip. The first semiconductor chip comprises a first surface in which a circuit unit is formed and a second surface in which a first cooling path is formed, and the second semiconductor chip comprises a first surface in which a circuit unit is formed and a second surface in which a second cooling path is formed. The second surface of the first semiconductor chip and the second surface of the second semiconductor chip are bonded to each other, and a third cooling path is formed in the middle of the stack-type semiconductor chip using the first and second cooling paths. Warpage of the stack-type semiconductor device is suppressed and heat is easily dissipated.Type: GrantFiled: May 21, 2007Date of Patent: December 1, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Hyun-Soo Chung, Cha-Jea Jo, Dong-Ho Lee, Seong-Deok Hwang
-
Publication number: 20090278561Abstract: The probe card is comprised of a probe card wafer, a plurality of through via electrodes penetrating the probe card wafer; and a plurality of redistributed wiring probe needle structures, each being connected to the through via electrodes protruding from a surface of the probe card wafer.Type: ApplicationFiled: December 8, 2008Publication date: November 12, 2009Inventors: Cha-jea Jo, Tae-gyeong Chung, Hoon-jung Kim, Nam-seog Kim, Chang-seong Jeon
-
Publication number: 20090230549Abstract: A flip chip package may include a substrate, a semiconductor chip, main bump structures and auxiliary bump structures. The substrate has a circuit pattern. The semiconductor chip is arranged over the substrate. The semiconductor chip includes a body having semiconductor structures, main pads electrically connected to the semiconductor structures to mainly control the semiconductor structures, and auxiliary pads electrically connected to the semiconductor structures to provide auxiliary control of the semiconductor structures. The main bump structures are interposed between the semiconductor chip and the substrate to electrically connect the circuit pattern with the main pads. The auxiliary bump structures can be interposed between the semiconductor chip and the substrate to electrically connect the circuit pattern with the auxiliary pads.Type: ApplicationFiled: March 11, 2009Publication date: September 17, 2009Applicant: Samsung Electronics Co., LtdInventors: Jong-Joo Lee, Tae-Joo Hwang, Cha-Jea Jo
-
Publication number: 20080230923Abstract: A chip stack package includes a substrate, a plurality of chips, a plurality of adhesive layers and a plug. The substrate has a wiring pattern and a seed layer formed on the wiring pattern. Each of the chips has an electrode pad and a first through-hole that penetrates the electrode pad. The chips are stacked such that the first through-holes are aligned on the seed layer of the substrate. The adhesive layers are interposed between the substrate and one of the chips, as well as between the chips. Each of the adhesive layers has a second through-hole connected to the first through-hole. The plug fills up the first through-holes and the second through-holes and electrically connects the electrode pads to the wiring pattern of the substrate. A cross-sectional area of the plug in the second through-holes may be larger than that of the plug in the first through-holes.Type: ApplicationFiled: March 19, 2008Publication date: September 25, 2008Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Cha-Jea JO, Myung-Kee CHUNG, Nam-Seog KIM, In-Young LEE, Seok-Ho KIM, Ho-Jin LEE, Ju-Il CHOI, Chang-Woo SHIN
-
Publication number: 20080157287Abstract: A semiconductor device and methods of forming the same are provided. The methods may include forming a hole in a preliminary semiconductor substrate, forming an insulating layer in the hole of the preliminary semiconductor substrate, forming a plating conductive layer on the insulating layer and the preliminary semiconductor substrate, forming a seed metal layer contacting the plating conductive layer at a lower portion of the hole and growing the seed metal layer to form a through-silicon via (TSV). The TSV may be formed through an electroplating process such that the seed metal layer grows from the lower portion of the hole to an upper portion of the hole.Type: ApplicationFiled: January 2, 2008Publication date: July 3, 2008Inventors: Ju-Il Choi, Cha-Jea Jo, Seok-Ho Kim, Chang-Woo Shin
-
Publication number: 20080157332Abstract: A stacked semiconductor package may include: a substrate; semiconductor packages stacked on the substrate; an interconnection member formed on edges of the semiconductor packages; and a conductive reinforcement member formed on the interconnection member. Each of the semiconductor packages may include a conductive line. The interconnection member may electrically connect the conductive line of the semiconductor packages to the conductive line of at least one other semiconductor package.Type: ApplicationFiled: December 12, 2007Publication date: July 3, 2008Inventors: Cha-Jea Jo, Seok-Ho Kim, Ju-Il Choi, Chang-Woo Shin
-
Publication number: 20080141933Abstract: Provided is a semiconductor plating system for plating a semiconductor object with a desired layer. The semiconductor plating system include a plating tank configured to accommodate a plating solution for use in plating the semiconductor object, and a plating solution induction device configured to induce the plating solution to spirally flow toward the semiconductor object.Type: ApplicationFiled: November 16, 2007Publication date: June 19, 2008Inventors: Cha-jea Jo, Joong-hyun Baek, Hee-jin Lee, Ku-young Kim, Ju-il Choi
-
Publication number: 20080096315Abstract: Provided is a stacked chip package and a method for forming the same. A spacer is formed on a side of an upper chip. A conductive line is formed on the spacer to electrically connect upper and lower chips. The reliability of the stacked chip package is improved because wire bonding is not used to electrically connect the upper and lower chips. Further, the overall size of the stacked chip package can be reduced as the height of bonding wire loops does not contribute to the overall stacked chip package height.Type: ApplicationFiled: January 15, 2007Publication date: April 24, 2008Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Se-Young JEONG, Nam-Seog KIM, Cha-Jea JO, Jong-Ho LEE, Myeong-Soon PARK
-
Publication number: 20070267738Abstract: Provided is a semiconductor device having a cooling path on its bottom surface. The stack-type semiconductor device having a cooling path comprises a stack-type semiconductor chip comprising a first semiconductor chip and a second semiconductor chip. The first semiconductor chip comprises a first surface in which a circuit unit is formed and a second surface in which a first cooling path is formed, and the second semiconductor chip comprises a first surface in which a circuit unit is formed and a second surface in which a second cooling path is formed. The second surface of the first semiconductor chip and the second surface of the second semiconductor chip are bonded to each other, and a third cooling path is formed in the middle of the stack-type semiconductor chip using the first and second cooling paths. Warpage of the stack-type semiconductor device is suppressed and heat is easily dissipated.Type: ApplicationFiled: May 21, 2007Publication date: November 22, 2007Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyun-Soo CHUNG, Cha-Jea JO, Dong-Ho LEE, Seong-Deok HWANG