Patents by Inventor Chakravarthy Gopalan
Chakravarthy Gopalan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11056646Abstract: An integrated circuit device can include a plurality of access transistors formed in a substrate having control terminals connected to word lines that extend in a first direction; a plurality of two-terminal programmable impedance elements formed over the substrate; at least one conductive plate structure formed on and having a common conductive connection to, the programmable impedance elements, and extending in at least the first direction; a plurality of storage contacts that extend from a first current terminal of each access transistor to one of the programmable impedance elements; a plurality of bit lines formed over the at least one conductive plate structure, the bit lines extending in a second direction different from the first direction; and a plurality of bit line contacts that extend from a second current terminal of each access transistor through openings in the at least one plate structure to one of the bit lines.Type: GrantFiled: July 20, 2016Date of Patent: July 6, 2021Assignee: Adesto Technologies CorporationInventors: Mark T. Ramsbey, Venkatesh P. Gopinath, Jeffrey Allan Shields, Kuei Chang Tsai, Chakravarthy Gopalan, Michael A. Van Buskirk
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Patent number: 10147877Abstract: In fabricating a memory device, a first electrode is provided. An oxide layer is provided on the first electrode. A second electrode is provided on the oxide layer. In a further method of fabricating a memory device, a first electrode is provided. An oxide layer is provided on the first electrode, the oxide layer comprising an oxygen deficiency and/or defects therein. A second electrode is then provided on the oxide layer.Type: GrantFiled: September 7, 2016Date of Patent: December 4, 2018Assignee: Cypress Semiconductor CorporationInventors: Matthew Buynoski, Seungmoo Choi, Chakravarthy Gopalan, Dongxiang Liao, Christie Marrian
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Publication number: 20180205012Abstract: An integrated circuit device can include a plurality of access transistors formed in a substrate having control terminals connected to word lines that extend in a first direction; a plurality of two-terminal programmable impedance elements formed over the substrate; at least one conductive plate structure formed on and having a common conductive connection to, the programmable impedance elements, and extending in at least the first direction; a plurality of storage contacts that extend from a first current terminal of each access transistor to one of the programmable impedance elements; a plurality of bit lines formed over the at least one conductive plate structure, the bit lines extending in a second direction different from the first direction; and a plurality of bit line contacts that extend from a second current terminal of each access transistor through openings in the at least one plate structure to one of the bit lines.Type: ApplicationFiled: July 20, 2016Publication date: July 19, 2018Inventors: Mark T. Ramsbey, Venkatesh P. Gopinath, Jeffrey Allan Shields, Kuei Chang Tsai, Chakravarthy Gopalan, Michael A. Van Buskirk
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Publication number: 20160380195Abstract: In fabricating a memory device, a first electrode is provided. An oxide layer is provided on the first electrode. A second electrode is provided on the oxide layer. In a further method of fabricating a memory device, a first electrode is provided. An oxide layer is provided on the first electrode, the oxide layer comprising an oxygen deficiency and/or defects therein. A second electrode is then provided on the oxide layer.Type: ApplicationFiled: September 7, 2016Publication date: December 29, 2016Inventors: Matthew BUYNOSKI, Seungmoo Choi, Chakravarthy Gopalan, Dongxiang Liao, Christie Marrian
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Patent number: 9461247Abstract: In fabricating a memory device, a first electrode is provided. An alloy is formed thereon, and the alloy is oxidized to provide an oxide layer. A second electrode is provided on the oxide layer. In a further method of fabricating a memory device, a first electrode is provided. Oxide is provided on the first electrode, and an implantation step in undertaken to implant material in the oxide to form a layer including oxide and implanted material having an oxygen deficiency and/or defects therein. A second electrode is then formed on the layer.Type: GrantFiled: February 2, 2015Date of Patent: October 4, 2016Assignee: Cypress Semiconductor CorporationInventors: Matthew Buynoski, Seungmoo Choi, Chakravarthy Gopalan, Dongxiang Liao, Christie Marrian
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Patent number: 9401472Abstract: Programmable impedance elements structures, devices and methods are disclosed. Methods can include: forming a first electrode layer within an electrode opening that extends through a cap layer; planarizing to expose a top of the cap layer; cleaning the exposed top surface of the cap layer to remove residual species from previous process steps. Additional methods can include forming at least a base ion conductor layer having an active metal formed therein that may ion conduct within the ion conductor layer; and forming an inhibitor material that mitigates agglomeration of the active metal within the base ion conductor layer as compared to the active metal alone. Programmable impedance elements and/or devices can have switching material and electrodes parallel to both bottoms and sides of a cell opening formed in a cell dielectric. Other embodiments can include an ion conductor layer having an alloy of an active metal, or two ion conductor layers in contact with an active electrode.Type: GrantFiled: September 23, 2011Date of Patent: July 26, 2016Assignee: Adesto Technologies CorporationInventors: Chakravarthy Gopalan, Antonio R. Gallo, Yi Ma
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Patent number: 9391270Abstract: A memory device can include a plurality of memory cells formed over a substrate, each memory cell including a tunnel access device that enables current flow in at least one direction predominantly due to tunneling, and a storage element programmable between different impedance states by a reduction-oxidation reaction within at least one memory layer formed between two electrodes; wherein the tunneling access device and programmable impedance element are vertically stacked over one another.Type: GrantFiled: October 31, 2014Date of Patent: July 12, 2016Assignee: Adesto Technologies CorporationInventors: Venkatesh P. Gopinath, Jeffrey Allan Shields, Yi Ma, Chakravarthy Gopalan, Ming Kwon, John Dinh
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Patent number: 9306161Abstract: A method of forming a conductive bridging memory cell can include forming an active electrode layer above a barrier layer formed on a lower conductive layer; forming at least one ion conductor layer over an active electrode layer; incorporating conductive ions into the ion conductor layer to create a switch memory layer that changes impedance in response to an electric field; and the active electrode layer is a source of conductive ions for the ion conductor, and the barrier layer substantially prevents a movement of conductive ions therethrough.Type: GrantFiled: March 18, 2013Date of Patent: April 5, 2016Assignee: Adesto Technologies CorporationInventors: Yi Ma, Chakravarthy Gopalan, Antonio R. Gallo, Janet Wang
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Publication number: 20160043310Abstract: A memory element can include a first electrode comprising at least a first element; a second electrode formed of a conductive material; and a memory layer comprising a memory material programmable between different resistance states. The first element can be ion conductible within the memory material. A second electrode can include an interface layer in contact with the memory layer. The interface layer being formed by inclusion of at least one modifier element not present in a remainder of the second electrode and not ion conductible within the memory material.Type: ApplicationFiled: July 4, 2015Publication date: February 11, 2016Inventors: Chakravarthy Gopalan, Wei Ti Lee, Yi Ma, Jeffrey Allan Shields
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Patent number: 9099633Abstract: A memory element can include a first electrode; a second electrode; and a memory material programmable between different resistance states, the memory material disposed between the first electrode and the second electrode and comprising a solid electrolyte with at least one modifier element formed therein; wherein the first electrode is an anode electrode that includes an anode element that is ion conductible in the solid electrolyte, the anode element being different than the modifier element.Type: GrantFiled: March 25, 2013Date of Patent: August 4, 2015Assignee: Adesto Technologies CorporationInventors: Chakravarthy Gopalan, Wei Ti Lee, Yi Ma, Jeffrey Allan Shields
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Publication number: 20150144857Abstract: In fabricating a memory device, a first electrode is provided. An alloy is formed thereon, and the alloy is oxidized to provide an oxide layer. A second electrode is provided on the oxide layer. In a further method of fabricating a memory device, a first electrode is provided. Oxide is provided on the first electrode, and an implantation step in undertaken to implant material in the oxide to form a layer including oxide and implanted material having an oxygen deficiency and/or defects therein. A second electrode is the formed on the layer.Type: ApplicationFiled: February 2, 2015Publication date: May 28, 2015Inventors: Matthew BUYNOSKI, Seungmoo CHOI, Chakravarthy GOPALAN, Dongxiang LIAO, Christie MARRIAN
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Patent number: 8946020Abstract: In fabricating a memory device, a first electrode is provided. An alloy is formed thereon, and the alloy is oxidized to provide an oxide layer. A second electrode is provided on the oxide layer. In a further method of fabricating a memory device, a first electrode is provided. Oxide is provided on the first electrode, and an implantation step in undertaken to implant material in the oxide to form a layer including oxide and implanted material having an oxygen deficiency and/or defects therein. A second electrode is then formed on the layer.Type: GrantFiled: September 6, 2007Date of Patent: February 3, 2015Assignee: Spansion, LLCInventors: Matthew Buynoski, Seungmoo Choi, Chakravarthy Gopalan, Dongxiang Liao, Christie Marrian
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Patent number: 8941089Abstract: In accordance with an embodiment of the present invention, a resistive switching device includes an opening disposed within a first dielectric layer, a conductive barrier layer disposed on sidewalls of the opening, a fill material including an inert material filling the opening. A solid electrolyte layer is disposed over the opening. The solid electrolyte contacts the fill material but not the conductive barrier layer. A top electrode is disposed over the solid electrolyte.Type: GrantFiled: February 14, 2013Date of Patent: January 27, 2015Assignee: Adesto Technologies CorporationInventors: Chakravarthy Gopalan, Jeffrey Shields, Venkatesh Gopinath, Janet Siao-Yian Wang, Kuei-Chang Tsai
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Patent number: 8866122Abstract: In one embodiment, a resistive switching device includes a bottom electrode, a switching layer, a buffer layer, and a top electrode. The switching layer is disposed over the bottom electrode. The buffer layer is disposed over the switching layer and provides a buffer of ions of a memory metal. The buffer layer includes an alloy of the memory metal with an alloying element, which includes antimony, tin, bismuth, aluminum, germanium, silicon, or arsenic. The top electrode is disposed over the buffer layer and provides a source of the memory metal.Type: GrantFiled: June 14, 2012Date of Patent: October 21, 2014Assignee: Adesto Technologies CorporationInventors: Wei Ti Lee, Chakravarthy Gopalan, Yi Ma, Kuei-Chang Tsai, Jeffrey Shields, Janet Wang
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Publication number: 20140293676Abstract: A memory element programmable between different impedance states can include a first electrode; a switching layer formed in contact with the first electrode and including at least one metal oxide; and a buffer layer in contact with the switching layer. A buffer layer can include a first metal, tellurium, a third element, and a second metal distributed within the buffer layer. A second electrode can be in contact with the buffer layer.Type: ApplicationFiled: March 3, 2014Publication date: October 2, 2014Inventors: Wei Ti Lee, Janet Wang, Chakravarthy Gopalan, Jeffrey Allan Shields, Yi Ma, Kuei Chang Tsai, John Sanchez, John Ross Jameson, Michael Van Buskirk, Venkatesh P. Gopinath
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Patent number: 8847192Abstract: In accordance with an embodiment of the present invention, a resistive switching device comprises a bottom electrode, a switching layer disposed over the bottom electrode, and a top electrode disposed over the switching layer. The top electrode comprises an alloy of a memory metal and an alloying element. The top electrode provides a source of the memory metal. The memory metal is configured to change a state of the switching layer.Type: GrantFiled: July 25, 2012Date of Patent: September 30, 2014Assignees: Adesto Technologies France SARL, Adesto Technologies CorporationInventors: Wei Ti Lee, Chakravarthy Gopalan, Yi Ma, Jeffrey Shields, Philippe Blanchard, John Ross Jameson, Foroozan Sarah Koushan, Janet Wang, Mark Kellam
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Patent number: 8829482Abstract: A programmable impedance memory device structure can include a multi-layer variable impedance memory element formed on a planar surface of a first barrier layer, the multi-layer variable impedance memory element comprising a plurality of layers substantially parallel to the planar surface, including a memory material layer in contact with the planar surface, the first barrier layer being formed above a first insulating layer; and a second barrier layer formed over the memory element having a top surface substantially parallel with the planar surface. The first and second barrier layers can have lower mobility rates for at least one element within the memory material layer than the first insulating layer, and the memory material layer can be programmable by application of an electrical field between at least two different impedance states.Type: GrantFiled: September 23, 2011Date of Patent: September 9, 2014Assignee: Adesto Technologies CorporationInventors: Antonio R. Gallo, Chakravarthy Gopalan, Yi Ma
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Patent number: 8816314Abstract: A memory element can include an opening formed within at least one insulating layer formed on an etch stop layer that exposes a first electrode portion and the etch stop layer at a bottom of the opening; a second electrode portion, formed on at least a side surface of the opening and in contact with the first electrode portion, the second electrode portion not filling the opening and being substantially not formed over a top surface of the at least one insulating layer; and at least one memory layer formed on a top surface of the at least one insulating layer and in contact with the second electrode portion, the at least one memory layer being reversibly programmable between at least two impedance states. Methods of forming such memory elements are also disclosed.Type: GrantFiled: May 12, 2012Date of Patent: August 26, 2014Assignee: Adesto Technologies CorporationInventor: Chakravarthy Gopalan
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Publication number: 20130285004Abstract: A memory element can include a first electrode; a second electrode; and a memory material programmable between different resistance states, the memory material disposed between the first electrode and the second electrode and comprising a solid electrolyte with at least one modifier element formed therein; wherein the first electrode is an anode electrode that includes an anode element that is ion conductible in the solid electrolyte, the anode element being different than the modifier element.Type: ApplicationFiled: March 25, 2013Publication date: October 31, 2013Inventors: Chakravarthy Gopalan, Wei Ti Lee, Yi Ma, Jeffrey Allan Shields
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Patent number: 8426839Abstract: A conductive bridging memory cell may include an ion conductor layer formed over an active electrode that is a source of conductive ions for the ion conductor; a conductive layer; and a barrier layer formed below the active layer and in contact with the conductive, the barrier layer substantially preventing a movement of conductive ions therethrough.Type: GrantFiled: April 26, 2010Date of Patent: April 23, 2013Assignee: Adesto Technologies CorporationInventors: Yi Ma, Chakravarthy Gopalan, Antonio R. Gallo, Janet Wang