PROGRAMMABLE RESISTANCE MEMORY ELEMENTS WITH ELECTRODE INTERFACE LAYER AND MEMORY DEVICES INCLUDING THE SAME
A memory element can include a first electrode comprising at least a first element; a second electrode formed of a conductive material; and a memory layer comprising a memory material programmable between different resistance states. The first element can be ion conductible within the memory material. A second electrode can include an interface layer in contact with the memory layer. The interface layer being formed by inclusion of at least one modifier element not present in a remainder of the second electrode and not ion conductible within the memory material.
This application is a continuation of U.S. patent application Ser. No. 13/850,267 filed on Mar. 25, 2013, which claims the benefit of U.S. provisional patent application Ser. No. 61/615,837, filed on Mar. 26, 2012, the contents all of which are incorporated by reference herein.
TECHNICAL FIELDThe present disclosure relates generally to memory devices with programmable impedance elements, and more particularly to memory elements that can program a solid electrolyte layer between different resistance states.
BACKGROUNDConventional conductive bridging random access memory (CBRAM) devices can include CBRAM type elements that can be placed into a low resistance state with a programming operation, and a high resistance state with an erase operation. Conventionally, after a CBRAM device has been fabricated, but before it is programmed or erased to store data for the very first time (i.e., the CBRAM elements are “fresh” elements), the CBRAM device is subject to a “forming” step. It is believed that the forming step can create an initial conductive path (i.e., filament) through a solid electrolyte material, which can be recreated, in some fashion, in subsequent programming operations (and dissolved in erase operations).
A forming step can take a relatively large amount of time in an integrated circuit manufacturing flow, and thus can present a production bottleneck. The amount of time consumed in a forming step can be exacerbated by the presence of “reverse programming”. Reverse programming can occur when erase conditions are applied to a CBRAM type element, but the element enters a low resistance state, instead of a desired high resistance state. If reverse programming occurs, it can take a substantial amount of time to bring the CBRAM elements from the reverse programmed state to a proper erased state.
In some conventional CBRAM devices, the effects of a forming step can be reversed or reduced if a device is subject to a heat cycle (such as a solder reflow on a packaged device).
Embodiments described herein show memory elements and manufacturing methods that include a memory layer between an anode electrode and a cathode electrode. A memory layer of a memory element can have a modifier material formed therein, which can result in the memory element having a suitable programming response without the need for a conventional forming step.
In very particular embodiments, memory elements can be conductive bridging random access memory (CBRAM) type cells, programmable between two or more resistance states.
In the various embodiments, like features may be referred to by the same reference character but with a first characters corresponding to the figure number.
A cathode electrode 102 can be formed from one or more conductive materials. A cathode electrode 102 can include any suitable material used to form interconnections, contacts, or vias in an integrated circuit device. In very particular embodiments, a cathode electrode 102 can be formed from and of: tungsten, titanium, titanium nitride, aluminum, tantalum, or tantalum nitride.
An interface layer 104 can be formed from a solid electrolyte with one or more modifier materials. In some embodiments, a memory element 100 can be a CBRAM element, and creating an interface layer 104 with modifier materials can alter the cathode-memory layer interface, enabling CBRAM elements to function without a conventional forming step.
In some embodiments, an interface layer 104 can include a chalcogen based solid electrolyte (e.g., a chalcogenide), a metal oxide, or a combination thereof. In a particular embodiment, a solid electrolyte can include germanium sulfide (GeS2), germanium—sulfur compounds of different stoichiometries (GeSx) and/or germanium selenium compounds (e.g., GeSe).
In some embodiments a modifier material added to a solid electrolyte can include a metal. A modifier metal can be a transition metal, including but not limited to copper (Cu), tantalum (Ta) or ruthenium (Ru),as well as the rare earth elements. A modifier can also include a post-transition metal such as aluminum (Al), as but one example. Post-transition metals are metals from those periodic table groups that occur after the transition metal groups (i.e., groups IIIA, IVA and VA), and include alumimun (Al), gallium (Ga), indium (In), thallium (TI), tin (Sn), lead (Pb) and bismuth (Bi).
In one very particular embodiment, an interface layer can include GeSx with Cu as a modifier metal, at 0.1% to 50% (atomic percent).
As understood from above, other embodiments can include a metal oxide with a modifier metal formed therein.
As will be shown below, inclusion of a modifier metal in an interface layer may make it possible to program and erase the memory element without a conventional forming step.
While modifier materials can include metals incorporated into a solid electrolyte, in other embodiments, a modifier material can be a non-metal. In very particular embodiments, a modifier non-metal can include oxygen (O) or nitrogen (N), as but two possible examples. In other embodiments, a modifier non-metal can include a semiconductor or metalloid, such as silicon (Si) or Ge (where Ge is not part of the solid electrolyte material),
In one very particular embodiment, an interface layer can include GeSx with N as a modifier metal, at 0.1% to 40% (atomic percent).
Referring still to
In some embodiments, a total thickness of memory layer 106 and interface layer 104 can be in the range of 3 to 1000 angstroms (Å).
An anode electrode 108 can be formed from one or more metals that ion conduct within memory layer 106 and interface layer 104. However, when a modifier metal is included in interface layer 104, such a metal can be different than the anode metal. In one very particular embodiment, an anode electrode 108 can be formed of silver (Ag), while an interface layer 104 can be formed of GeSx with Cu as a modifier metal.
However, unlike
In some embodiments, a total thickness of memory layer 206 and interface layer 204 can be in the range of 3 to 1000 angstroms (Å). An interface layer 204 can have a thickness less than that of memory layer 206. In particular embodiments, an interface layer 204 have less than ½ the thickness of memory layer 206, preferably less than ¼ the thickness of memory layer 206.
While the embodiments above have shown modifications of a cathode-memory layer interface with a layer formed on a cathode electrode, other embodiments can modify a cathode electrode material to form an interface layer. One such embodiment is shown in
Unlike
In some embodiments, an interface layer 304 can extend into a cathode electrode 302 to a depth in the range of 3 to 1000 angstroms (Å).
A memory layer 306 can include one or more solid electrolytes. In some embodiments, a solid electrolyte of interface layer 304 can include a chalcogenide, a metal oxide, or combinations thereof. In a particular embodiment, a solid electrolyte can include GeS2, GeSx and/or GeSe.
While the embodiments of
In addition or alternatively, an interface layer 404 can be deposited with reactive sputtering. More particularly, one or more gases containing the modifier materials can be introduced into the plasma. Reactive sputtering can be a suitable method for modifier materials that are non-metals (e.g., O, N). In a particular embodiment, a reactive sputtering process can sputter GeSx and/or GeS2 in a plasma formed by argon gas (Ar) together with nitrogen gas (N2) providing non-metal modifier N. A flow ratio between N2:Ar can be in the range of 0.05 to 2.
It is understood that an interface layer 404 can be formed form any other suitable method. Such alternate methods can include, but are not limited to: evaporative methods, chemical vapor deposition (CVD), including plasma enhanced CVD, atomic layer deposition, or electroplating, as but a few examples.
In other embodiments, an interface layer 504 can be formed as a separate layer than memory layer 506. Further, a solid electrolyte material of memory layer 506 can be different than that of interface layer 504.
In alternate embodiments, an interface layer can be created with methods noted in
While the embodiments of
Like
An interface layer 704 can be formed from the same materials, and subject to the same variation as noted for interface layer 204 shown in
Unlike
In one very particular embodiment, an anode electrode 808 can be formed of silver, and an interface layer 804 can be formed of copper.
In some embodiments, an interface layer 804 can occupy an initial thickness of anode electrode 808 in the range of 3 to 1000 angstroms (Å).
A memory layer 806 can include one or more solid electrolytes. In some embodiments, a solid electrolyte of interface layer 804 can include a chalcogenide, a metal oxide, or combinations thereof. In a particular embodiment, a solid electrolyte can include GeS2, GeSx and/or GeSe.
In particular embodiments, an interface layer can be created with methods noted in
In alternate embodiments, a surface treatment can include any of: depositing a modifier material; subjecting the surface to a temperature cycle in an environment that includes the modifier material; oxidizing the surface; ion implanting into the surface; and exposing the surface to a plasma having a gas that includes the modifier material.
As shown in
As shown, page program times can be as short as 2 ms. This is comparable to conventional elements that have been subject to a forming step.
As shown, the introduction of a nitride GeSx interface layer can provide program/erase times comparable to conventional elements subject to a forming step, with very little RPG.
It is understood that the results shown in
Embodiments of the invention can improve erase times for fresh elements by reducing and/or eliminating reverse programming. Embodiments may also enable memory elements with solid electrolyte memory layers to be fabricated for use without a forming step, or with a forming step that is shorter than conventional approaches.
It should be appreciated that in the foregoing description of exemplary embodiments, various features are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure aiding in the understanding of one or more of the various inventive aspects. This method of disclosure, however, is not to be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.
It is also understood that the embodiments of the invention may be practiced in the absence of an element and/or step not specifically disclosed. That is, an inventive feature of the invention can be elimination of an element.
Accordingly, while the various aspects of the particular embodiments set forth herein have been described in detail, the present invention could be subject to various changes, substitutions, and alterations without departing from the spirit and scope of the invention.
Claims
1. A memory element, comprising:
- a first electrode comprising at least a first element;
- a second electrode formed of a conductive material; and
- a memory layer disposed between the first electrode and a second electrode, the memory layer comprising a memory material programmable between different resistance states, the first element being ion conductible within the memory material; wherein
- the second electrode includes an interface layer on a surface of the second electrode in contact with the memory layer, the interface layer formed by inclusion of at least one modifier element not present in a remainder of the second electrode, the modifier element not being ion conductible within the memory material.
2. The memory element of claim 1, wherein:
- the modifier element is a non-metal.
3. The memory element of claim 2, wherein:
- the modifier element is nitrogen.
4. The memory element of claim 2, wherein:
- the modifier element is oxygen.
5. The memory element of claim 4, wherein:
- the second electrode comprises a metal; and
- the interface layer comprises an oxide of the metal.
6. The memory element of claim 2, wherein:
- the modifier element is a semiconductor that is not included in the memory material.
7. The memory element of claim 1, wherein:
- the interface layer has a thickness less than one half the thickness of the memory layer.
8. A memory element, comprising:
- a first electrode comprising at least a first element;
- a second electrode comprising at least second element;
- a memory layer disposed between the first electrode and a second electrode, the memory layer comprising a memory material programmable between different resistance states, the first element being ion conductible within the memory material; and
- an interface layer on a surface of the second electrode in contact with the memory layer, the interface layer formed by inclusion of at least one modifier element not present in a remainder of the second electrode, the modifier element being a non-metal.
9. The memory element of claim 8, wherein:
- the modifier element is selected from the group of: oxygen and nitrogen.
10. The memory element of claim 9, wherein:
- the interface layer comprises an oxide of the second element.
11. The memory element of claim 9, wherein:
- the interface layer comprises a nitride of the second element.
12. The memory element of claim 8, wherein:
- the modifier element is a semiconductor.
13. The memory element of claim 8, wherein:
- the first electrode, second electrode and memory layer are vertically stacked, the first electrode being a top electrode and the second electrode being a bottom electrode.
14. A method, comprising:
- forming a first electrode;
- forming an interface layer that extends into the first electrode by inclusion of at least one modifier element not present in a remainder of the second electrode;
- forming a memory layer in contact with the interface layer, the memory layer comprising a memory material programmable between different resistance states; and
- forming a second electrode comprising a first element that is ion conductible within the memory material; wherein the modifier element is not ion conductible within the memory material.
15. The method of claim 14, wherein:
- forming the interface layer includes treating an exposed surface of the first electrode.
16. The method of claim 15, wherein:
- treating the exposed surface of the first electrode includes subjecting the surface to a temperature cycle.
17. The method of claim 15, wherein:
- treating the exposed surface of the first electrode includes oxidizing the surface.
18. The method of claim 15, wherein:
- treating the exposed surface of the first electrode includes implanting atoms of the modifier element into the surface.
19. The method of claim 15, wherein:
- treating the exposed surface of the first electrode includes exposing the surface to a plasma that includes a gas comprising the modifier element.
20. The method of claim 14, wherein:
- forming the interface layer includes adding the modifier element in situ as the first electrode is formed.
Type: Application
Filed: Jul 4, 2015
Publication Date: Feb 11, 2016
Inventors: Chakravarthy Gopalan (Santa Clara, CA), Wei Ti Lee (San Jose, CA), Yi Ma (Santa Clara, CA), Jeffrey Allan Shields (Sunnyvale, CA)
Application Number: 14/791,412