Abstract: A shift register is provided in which leakage of charges from a voltage at a set node is prevented to stabilize an output from a stage. The shift register includes stages for sequentially outputting scan pulses. An nth one of the stages includes a node controller for controlling voltages at nodes, and an output unit for outputting any one of a corresponding one of the scan pulses and a first discharging voltage according to the voltages at the nodes. The nodes include set and reset nodes. The node controller of the nth stage includes a first switching device controlled by a voltage supplied to the reset node for supplying a second discharging voltage to the set node, and an inverter circuit controlled by a voltage supplied to the set node for supplying any one of a charging voltage and a third discharging voltage to the reset node.

Abstract: A method, a terminal, and a system for automatically transferring information about a fall or overturn accident using a smart phone are provided. The method includes, by an elder customer terminal assigned to an elder customer, detecting a fall or overturn accident via a 3-axis acceleration sensor, and sending a fall or overturn detection message, including its own ID information and a fall or overturn state, to a controller based on the detection, by the controller, receiving the fall or overturn detection message, generating fall or overturn detection information based on the received fall or overturn detection message, and registering the fall or overturn detection information with a database, and, by the controller, configuring a message based on the fall or overturn detection information, and notifying the smart phone of the message based on the fall or overturn detection information.

Abstract: An FFS mode LCD and a fabrication method thereof are provided. The fabrication method comprises: etching a common electrode material and a gate metal on a board at the same time through a first mask process; forming a gate insulating layer, an active layer and a source/drain metal on the board; forming a channel in a TFT part, forming an opening in the pixel area part by diffraction exposure and exposing a gate pad part through a second mask process; forming a passivation layer substantially on board, and forming a contact hole in TFT part, etching regions in pixel area part and exposing a gate pad and a data pad part through a third mask process; and forming a pixel electrode on regions of the TFT, pixel area part and opened regions of the gate pad and data pad part through a fourth mask process.

Abstract: A gate driving circuit includes a first clock generator to output n output control clock pulses having different phases; a second clock generator to create m*n output clock pulses having different phases and partially overlapped with one another in high periods thereof, to arrange the m*n output clock pulses in sequence of phase, to bind the m*n output clock pulses arranged in sequence of phase in units of n to generate m groups, each of which has n output clock pulses, and to output the m*n output clock pulses so that a rising edge of an output clock pulse having a k-th sequence of phase included in each group is located in a high period of an output control clock pulse having a k-th sequence of phase among the n output control clock pulses; and a shift register sequentially outputting a plurality of scan pulses.

Abstract: An apparatus and method for canceling a Direct Current (DC) offset in a Broadband Wireless Access (BWA) communication system are provided. The method includes canceling a DC offset by performing self-calibration in a modulator/demodulator (modem), attempting initial synchronization acquisition in the modem, and if the initial synchronization acquisition succeeds, canceling a DC offset by performing DC offset trace and cancellation.

Abstract: Circuits and methods for suppressing integrated circuit leakage currents are described. Many of these circuits and methods are particularly well-suited for use in dynamic memory circuits. Examples describe the use of power, ground, or both and power and ground source transistors used for generating virtual voltages. An aspect of the invention describes lowering refresh current. An aspect describes reducing the standby current. An aspect of the invention describes lowering leakage resulting from duplicated circuits, such as row decoders and word line drivers. An aspect describes methods of performing early wake-up of source transistors. A number of source transistor control mechanisms are taught. Circuit layouts methods are taught for optimizing integrated circuit layouts using the source transistors.

Abstract: A method of booting an information handling system including a volatile memory device to be selectively tested during a booting operation, the method comprising a step of reading current system configuration information from the information handling system, a step of comparing the current system configuration information with corresponding prestored system configuration information in a nonvolatile memory device, and a step of selectively performing a test for the volatile memory device according to a result of the comparison.

Abstract: An array substrate for an in-plane switching mode liquid crystal display device includes a substrate, a gate line disposed along a first direction on the substrate, a data line disposed along a second direction and crossing the gate line to define a pixel region, a thin film transistor connected to the gate line and the data line, pixel electrodes disposed in the pixel region and connected to the thin film transistor, common electrodes disposed in the pixel region and alternating with the pixel electrodes, a semiconductor layer underlying the data line and including a portion having a width greater than a width of the data line, and a first blocking pattern comprising an opaque material and disposed under the semiconductor layer.

Abstract: Disclosed herein is a shift register in which leakage of charges from a voltage at a set node is prevented to stabilize an output from a stage. The shift register includes a plurality of stages for sequentially outputting scan pulses. Each stage includes a node controller for controlling signal states of a set node and a reset node, and an output unit supplied with any one of a plurality of clock pulses having different phases. The output unit outputs the supplied clock pulse as a scan pulse through an output terminal thereof according to the signal states of the set node and reset node. The node controller includes a first discharging switching device which is turned on or off in response to a scan pulse from a downstream stage. The first discharging switching device is connected between any one of a plurality of clock transfer lines and the set node.

Abstract: A content sharing method of an intermediate node based on a content oriented network (CON) is provided. The method includes receiving, from a content requesting terminal, a proxy sharing request message with respect to a content including a content name of the content, the content including a plurality of data segments, generating data segment request messages with respect to each of the plurality of data segments corresponding to the content, in response to the reception of the proxy sharing request message, transmitting the data segment request messages to at least one terminal having the plurality of data segments, receiving the plurality of data segments from the at least one terminal, and transmitting the content to the content requesting terminal, using an aggregated data transmission scheme based on the received plurality of data segments.

Abstract: A method of manufacturing an LCD device is disclosed.

Abstract: Provided is a communication method of a terminal, including generating, based on a characteristic of an application executed by at least one terminal in a virtual group, a content request message to request content stored by one or more other terminals in the virtual group, and transmitting the content request message to an intermediate node managing the at least one terminal to receive the content stored by the one or more other terminals.

Abstract: An array substrate for an in-plane switching mode liquid crystal display device includes a substrate, a gate line disposed along a first direction on the substrate, a data line disposed along a second direction and crossing the gate line to define a pixel region, a thin film transistor connected to the gate line and the data line, pixel electrodes disposed in the pixel region and connected to the thin film transistor, common electrodes disposed in the pixel region and alternating with the pixel electrodes, a semiconductor layer underlying the data line and including a portion having a width greater than a width of the data line, and a first blocking pattern comprising an opaque material and disposed under the semiconductor layer.

Abstract: Various embodiments of a data transfer circuit of a semiconductor apparatus are disclosed. In one exemplary embodiment, the data transfer circuit may include a first data line, a second data line, a first transfer unit configured to amplify data on the first data line in response to a first control signal and transfer amplified data to the second data line, and a second transfer unit configured to electrically connect the first data line to the second data line in response to a second control signal.

Abstract: Provided is a method of controlling a home hub in a virtual group that may provide a geographical boundary about the virtual group by associating an identifier of a network of a virtual group included in an access point list with a name of the virtual group and a name of the home hub managing the virtual group, and may provide a terminal which moves to a visited virtual group with information about a network of the visited virtual group, thereby facilitating recognition of a virtual group and content sharing.

Abstract: Disclosed herein is a liquid crystal display device which is capable of reducing the number of data drive integrated circuits (ICs) to curtail a production cost. The liquid crystal display device includes a plurality of pixel cells formed respectively in areas defined by a plurality of gate lines and a plurality of data lines, a first unit pixel including at least three of the pixel cells, the at least three pixel cells being connected to different ones of the data lines, and a second unit pixel including at least three of the pixel cells other than the at least three pixel cells of the first unit pixel, the at least three pixel cells of the second unit pixel being connected respectively to the different data lines to which the at least three pixel cells of the first unit pixel are connected, wherein the first and second unit pixels are arranged in a direction of the data lines and connected to different ones of the gate lines.

Abstract: A method of communication for a terminal in a content-centric network is provided. The method includes suspending a data message associated with a content from being provided to a face before a handover when the handover is expected to occur in the terminal that requests the content, and transmitting, to a hub, a new interest message after the handover associated with the content so that the hub may provide the data message associated with the content to the face after the handover.

Abstract: Provided is a communication method of a hub that selects a transmission route from the hub to a receiving terminal of a receiving virtual group based on interface information about at least one interface which is available for use by the receiving terminal and is received from the receiving terminal and interface information about at least one interface which is available for use by a transmitting terminal of a transmitting virtual group and is received from the transmitting terminal.

Abstract: An array substrate for an in-plane switching mode liquid crystal display device includes a substrate, a gate line disposed along a first direction on the substrate, a data line disposed along a second direction and crossing the gate line to define a pixel region, a thin film transistor connected to the gate line and the data line, pixel electrodes disposed in the pixel region and connected to the thin film transistor, common electrodes disposed in the pixel region and alternating with the pixel electrodes, a semiconductor layer underlying the data line and including a portion having a width greater than a width of the data line, and a first blocking pattern comprising an opaque material and disposed under the semiconductor layer.

Abstract: A semiconductor memory device includes a strobe signal generator for receiving a write command and generating a write strobe signal that defines an activation period variably according to an operation frequency, and a data transfer unit for transferring data from an external device to an internal data line in response to the write strobe signal.