Abstract: A semiconductor memory device includes: a memory cell array region having a plurality of normal cell lines and a plurality of repair cell lines; a plurality of normal cell line selection units suitable for selecting the plurality of normal cell lines, respectively, in response to a local address; a plurality of repair cell line selection units suitable for selecting the plurality of repair cell lines, respectively, in place of normal cell line selection units corresponding to fail information of the local address; a fuse driving unit comprising a fuse array in which the fail information is programmed, suitable for disabling the normal cell line selection units corresponding to the fail information, and enabling normal cell line selection units unrelated to the fail information; and an address determination unit suitable for controlling the plurality of repair cell line selection units based on the fail information.

Abstract: A Peer-to-Peer (P2P)-based network apparatus and system is provided. The P2P-based network apparatus may sense the movement of a mobile station (MS), select a candidate proxy, and change a proxy of the MS to the candidate proxy.

Abstract: A data driving apparatus and method for a liquid crystal display (LCD) device is provided, the apparatus including: a liquid crystal panel; a timing controller configured to output control signals for controlling the driving of a gate driving unit and a data driving unit; a gate driving unit configured to output a gate on signal to gate lines of the liquid crystal panel; a data driving unit configured to drive data lines of the liquid crystal panel, the data driving unit providing an overdriving signal to at least one of a pair of pixel signals of the same polarity applied to adjacent data lines for supply to longitudinally adjacent pixels of the liquid crystal panel, and wherein the data driving unit drives the liquid crystal panel according to a longitudinal two-dot inversion polarity pattern.

Abstract: A content sharing method of an intermediate node based on a content oriented network (CON) is provided. The method includes receiving, from a content requesting terminal, a proxy sharing request message with respect to a content including a content name of the content, the content including a plurality of data segments, generating data segment request messages with respect to each of the plurality of data segments corresponding to the content, in response to the reception of the proxy sharing request message, transmitting the data segment request messages to at least one terminal having the plurality of data segments, receiving the plurality of data segments from the at least one terminal, and transmitting the content to the content requesting terminal, using an aggregated data transmission scheme based on the received plurality of data segments.

Abstract: An LCD device includes at least one data line, a plurality of first pixel cells connected in common to one side of the data line, a timing controller for alternately outputting first and second-polarity data signals at intervals of at least two successive periods, a data modulator for outputting the first and second-polarity data signals supplied from the timing controller, the data modulator modulating a grayscale value of one of the first and second-polarity data signals respectively supplied in two successive periods from the timing controller, and outputting the modulated data signal, and a data driver for receiving the first and second-polarity data signals from the data modulator, and alternately outputting the first and second-polarity data signals at intervals of at least two successive periods, to supply the first and second-polarity data signals to the data line.

Abstract: Disclosed herein is a shift register in which leakage of charges from a voltage at a set node is prevented to stabilize an output from a stage. The shift register includes a plurality of stages for sequentially outputting scan pulses. Each stage includes a node controller for controlling signal states of a set node and a reset node, and an output unit supplied with any one of a plurality of clock pulses having different phases. The output unit outputs the supplied clock pulse as a scan pulse through an output terminal thereof according to the signal states of the set node and reset node. The node controller includes a first discharging switching device which is turned on or off in response to a scan pulse from a downstream stage. The first discharging switching device is connected between any one of a plurality of clock transfer lines and the set node.

Abstract: Provided is a method of economically modifying low rank coal (LRC) to be high grade coal having minimized water re-absorption and minimized spontaneous ignition possibility while saving energy by coating heavy oil directly on coal without using solvent oil. Provides is a method of modifying coal using palm oil residue, including milling the coal, homogenously mixing the palm oil residue with the milled coal, melting the palm oil residue mixed with the coal so as to be coated on a surface of the coal, and simultaneously drying moisture in the coal, cooling the dried coal, and briquetting the cooled coal.

Abstract: A word line driving circuit includes, inter alia: a word line driving signal generator, a main word line enable signal controller, and a sub word line driver. The word line driving signal generator activates a word line boosting signal, a pre-main word line enable signal, and a word line off signal in response to an active signal and a precharge signal. The main word line enable signal controller receives the pre-main word line enable signal and outputs it as the main word line enable signal in response to a main word line test mode signal. The sub word line driver uses the word line boosting signal as a driving voltage, and drives a sub word line in response to the main word line enable signal and the word line off signal.

Abstract: A shift register is provided in which leakage of charges from a voltage at a set node is prevented to stabilize an output from a stage. The shift register includes stages for sequentially outputting scan pulses. An nth one of the stages includes a node controller for controlling voltages at nodes, and an output unit for outputting any one of a corresponding one of the scan pulses and a first discharging voltage according to the voltages at the nodes. The nodes include set and reset nodes. The node controller of the nth stage includes a first switching device controlled by a voltage supplied to the reset node for supplying a second discharging voltage to the set node, and an inverter circuit controlled by a voltage supplied to the set node for supplying any one of a charging voltage and a third discharging voltage to the reset node.

Abstract: Disclosed herein is a shift register in which leakage of charges from a voltage at a set node is prevented to stabilize an output from a stage. The shift register includes a plurality of stages for sequentially outputting scan pulses. Each stage includes a node controller for controlling signal states of a set node and a reset node, and an output unit supplied with any one of a plurality of clock pulses having different phases. The output unit outputs the supplied clock pulse as a scan pulse through an output terminal thereof according to the signal states of the set node and reset node. The node controller includes a first discharging switching device which is turned on or off in response to a scan pulse from a downstream stage. The first discharging switching device is connected between any one of a plurality of clock transfer lines and the set node.

Abstract: A reinforcing structure of a rear spring seat for a vehicle includes a rear spring seat mounted on a rear side member and outer and inner reinforcing members provided at the outside and inside of the rear spring seat, respectively, wherein a lower portion of the outer reinforcing member is extended to cover an outer lower end of the rear spring seat.

Abstract: Provided is a method of controlling a home hub in a virtual group that may provide a geographical boundary about the virtual group by associating an identifier of a network of a virtual group included in an access point list with a name of the virtual group and a name of the home hub managing the virtual group, and may provide a terminal which moves to a visited virtual group with information about a network of the visited virtual group, thereby facilitating recognition of a virtual group and content sharing.

Abstract: In a network system based on a content name, a terminal device may generate and transmit a block query requesting segments, and may receive segments corresponding to the block query.

Abstract: Disclosed herein is a shift register in which leakage of charges from a voltage at a set node is prevented to stabilize an output from a stage. The shift register includes a plurality of stages for sequentially outputting scan pulses. Each stage includes a node controller for controlling signal states of a set node and a reset node, and an output unit supplied with any one of a plurality of clock pulses having different phases. The output unit outputs the supplied clock pulse as a scan pulse through an output terminal thereof according to the signal states of the set node and reset node. The node controller includes a first discharging switching device which is turned on or off in response to a scan pulse from a downstream stage. The first discharging switching device is connected between any one of a plurality of clock transfer lines and the set node.

Abstract: Discussed herein is a shift register which is capable of stabilizing an output thereof. The shift register includes a plurality of stages for sequentially outputting scan pulses in such a manner that high durations of the scan pulses partially overlap with each other. Each of the stages includes a node controller for controlling a charging duration of a set node, and an output unit for outputting a corresponding one of the scan pulses through an output terminal for the charging duration of the set node.

Abstract: A decoder circuit, responsive to a burst sequence control signal, for accessing a memory location in a memory array. The decoder circuit receives an address signal and outputs a plurality of first select lines. Logic circuitry receives these first select lines and a burst sequence control signal and outputs a plurality of second select lines. When the bust sequence control signal is unasserted, the logic circuitry passes through to the plurality of second select lines the signals received on the plurality of first select lines. When the burst sequence control signal is asserted, the logic circuitry performs a logical operation on the signals received on the plurality of first select lines and outputs the result on the plurality of second select lines.

Abstract: Disclosed herein is a shift register in which leakage of charges from a voltage at a set node is prevented to stabilize an output from a stage. The shift register includes a plurality of stages for sequentially outputting scan pulses. Each stage includes a node controller for controlling signal states of a set node and a reset node, and an output unit supplied with any one of a plurality of clock pulses having different phases. The output unit outputs the supplied clock pulse as a scan pulse through an output terminal thereof according to the signal states of the set node and reset node. The node controller includes a first discharging switching device which is turned on or off in response to a scan pulse from a downstream stage. The first discharging switching device is connected between any one of a plurality of clock transfer lines and the set node.

Abstract: A gate driving circuit includes a first clock generator to output n output control clock pulses having different phases; a second clock generator to create m*n output clock pulses having different phases and partially overlapped with one another in high periods thereof, to arrange the m*n output clock pulses in sequence of phase, to bind the m*n output clock pulses arranged in sequence of phase in units of n to generate m groups, each of which has n output clock pulses, and to output the m*n output clock pulses so that a rising edge of an output clock pulse having a k-th sequence of phase included in each group is located in a high period of an output control clock pulse having a k-th sequence of phase among the n output control clock pulses; and a shift register sequentially outputting a plurality of scan pulses.

Abstract: Discussed herein is a shift register which is capable of stabilizing an output thereof. The shift register includes a plurality of stages for sequentially outputting scan pulses in such a manner that high durations of the scan pulses partially overlap with each other. Each of the stages includes a node controller for controlling a charging duration of a set node, and an output unit for outputting a corresponding one of the scan pulses through an output terminal for the charging duration of the set node.

Abstract: An apparatus and method for receiving data over a network are provided. The data reception apparatus may include a receiver, a congestion decision unit and a suspension session selector. The receiver is configured to receive segments of data, using sessions corresponding to data transmissions apparatuses. The congestion detection unit is configured to determine whether a network to be utilized by a corresponding segment is congested, based on a status of each of the sessions. The suspension selector is configured to select a suspension session from the sessions where the network is determined to be congested.