Abstract: A data storage device is provided. The data storage device includes a storage medium configured to store data blocks included in a stripe set, and a controller connected to the storage medium and configured to, decode a first data block disposed in a column among the data blocks, during a read operation of the first data block, and read first group data blocks disposed in the column among the data blocks, based on a read failure of the first data block.

Abstract: Provided are a multichip debugging method and a multichip system adopting the same. The multichip system includes: a first chip including a first debugging port and first identification (ID) information, a second chip including a second debugging port and second ID information, and a test access port (TAP) electrically connected to the first debugging port and the second debugging port and configured to connect to a test apparatus via the TAP.

Abstract: A data storage device includes a controller connected via a plurality of channels to a plurality of clusters, wherein each cluster comprises a scale-out device including a scale-out controller and a buffer. The scale-out controller is connected to a plurality of sub-channels, each one of the plurality of sub-channels connecting a group of non-volatile memory (NVM) devices, such that the scale-out controller controls execution of data processing operations directed to any one of the NVM devices and the buffer.

Abstract: A data storage device includes a first scale-out controller configured to control a first non-volatile memory and a first volatile memory, a second scale-out controller configured to control a second non-volatile memory and a second volatile memory, and a controller configured to set a first memory management policy for the first non-volatile memory to be different from a second memory management policy for the second non-volatile memory.

Abstract: The data storage device includes scale-out storage devices and a controller configured to assign commands to the scale-out storage devices and re-assign the commands assigned to the scale-out storage devices based on state information output from a first scale-out storage device among the scale-out storage devices. Each of the scale-out storage devices includes a volatile memory device, a non-volatile memory device, and a scale-out controller configured to control the volatile memory device and the non-volatile memory device.

Abstract: A scale-out device to control a group of non-volatile memory devices from among a plurality of non-volatile memory devices at a data storage device, includes a buffer and a scale-out controller. The buffer is configured to store address mapping information for the group of non-volatile memory devices, the group of non-volatile memory devices being a portion of the plurality of non-volatile memory devices at the data storage device. The scale-out controller is configured to control operation of only the group of non-volatile memory devices according to the address mapping information stored at the buffer.

Abstract: A method of operating a data compression device includes analyzing data using an analyzer and generating a result of the analysis, while the data is buffered by an input buffer, and selectively compressing the buffered data according to the result of the analysis. A data compression device includes a data pattern analyzer configured to analyze data transmitted to an input buffer, and generate an analysis code based on the analysis of the data; and a data compression manager configured to selectively compress the data in the input buffer based on the analysis code.

Abstract: A method of operating a data compression device includes analyzing data using an analyzer and generating a result of the analysis, while the data is buffered by an input buffer, and selectively compressing the buffered data according to the result of the analysis. A data compression device includes a data pattern analyzer configured to analyze data transmitted to an input buffer, and generate an analysis code based on the analysis of the data; and a data compression manager configured to selectively compress the data in the input buffer based on the analysis code.

Abstract: A method of operating a data compression device includes analyzing data using an analyzer and generating a result of the analysis, while the data is buffered by an input buffer, and selectively compressing the buffered data according to the result of the analysis. A data compression device includes a data pattern analyzer configured to analyze data transmitted to an input buffer, and generate an analysis code based on the analysis of the data; and a data compression manager configured to selectively compress the data in the input buffer based on the analysis code.

Abstract: A memory system includes: a memory controller including an error correction decoder. The error correction decoder includes: a demultiplexer adapted to receive data and demultiplex the data into a first set of data and a second set of data; first and second buffer memories for storing the first and second sets of data, respectively; an error detector; an error corrector; and a multiplexer adapted to multiplex the first set of data and the second set of data and to provide the multiplexed data to the error corrector. While the error corrector corrects errors in the first set of data, the error detector detects errors in the second set of data stored in the second buffer memory.

Abstract: There is provided to a method for encoding an LDPC (Low Density Parity Check) code using the result of checking a previously specified parity, including the steps of: forming a parity bit check matrix having a dual diagonal structure consisting of (N-K) rows for check nodes and (N-K) columns on the basis of the H matrix; calculating the values of all the parity bits by inserting a given binary value in sub-blocks, with the parity bit check matrix formed on the H matrix; if the values of the parity bits are incorrect, checking the parity bit corresponding to the sub-block located in the last part of the H matrix; searching the parity bit parts where the parity bit check result is represented as “1”; performing an XOR operation in sub-blocks on the parity bit part obtained through a simultaneous equation between the parity bits of the searched parity bit parts and the parity bit parts; and determining the value of the parity bit satisfying the condition that the value obtained by multiplying the H matrix by a c

Abstract: The present invention relates to a decoding device and method for a MIMO system. A linear process is applied to a received signal vector by using a channel matrix estimated from the received signal vector and a poly-diagonalized matrix, and a soft decision value is acquired through a trellis decode by using the linear process result. Since the linear preprocess is performed by using the poly-diagonalized matrix, it is possible to receive a MIMO signal having good packet error rate performance and less complexity. Also, since the tail-biting trellis decoding method is used based on the poly-diagonalized matrix that is generated by poly-diagonalizing the effective channel matrix during the process for eliminating the signal interference, the soft decision value for the symbol can be generated with a simple hardwired device and less operation complexity.

Abstract: A method of operating a data compression device includes analyzing data using an analyzer and generating a result of the analysis, while the data is buffered by an input buffer, and selectively compressing the buffered data according to the result of the analysis. A data compression device includes a data pattern analyzer configured to analyze data transmitted to an input buffer, and generate an analysis code based on the analysis of the data; and a data compression manager configured to selectively compress the data in the input buffer based on the analysis code.

Abstract: Provided are an apparatus for receiving signals in an OFDM communication system using multiple transmission/reception antennas and a method thereof. The method includes modulating a predetermined part of a data stream based on a multi-dimensional reception procedure to generate a first modulated data stream; regenerating a symbol corresponding to the modulated data stream; eliminating the regenerated symbol from a remained data stream; modulating the eliminated data stream to generate a second modulated data stream; and outputting an output signal obtained by serializing the first modulated data stream and the second modulated data stream.

Abstract: A multi-input multi-output system, receiving apparatus and method of receiving signals are provided. The multi-input multi-output system includes a transmitting apparatus configured to send signals coded through a double space time transmit diversity scheme while changing a phase and an antenna, and a receiving apparatus configured to, if a signal is received from the transmitting apparatus, estimate predetermined symbols by use of a maximum likelihood estimation scheme, estimate remaining symbols by use of a decision feedback equalization scheme, and to calculate a Log Likelihood Ratio (LLR) of each of the predetermined symbols and the remaining symbols, in which the LLR of the remaining symbol is calculated by switching a channel matrix vector (H) of the receiving signal.

Abstract: The present invention relates to an orthogonal frequency division multiplexing wireless local area network (LAN) transmitting/receiving system for providing expanded service coverage, and a method thereof. A first OFDM modulation is performed for an even-numbered time, and a second OFDM modulation is performed for an odd-numbered time. A transmitting frame including a plurality of signal fields according to the first and second OFDM modulation is transmitted. The receiving system determines whether a signal field is repeatedly generated in the frame. If the signal field is not repeatedly generated, corresponding demodulation is performed. If repeatedly performed, the signal field is demodulated by using first bit allocation information and second bit allocation information having a ½ value of the first bit allocation information. A data field is demodulated according to the demodulated signal field.

Abstract: A digital system design method uses a higher programming language. In order to realize a digital system, an algorithm is verified based on a program written by the higher programming language and a program is programmed considering the higher programming language-hardware characteristics before the program is written in the lower programming language, and thus conversion into the lower programming language may be easily performed.

Abstract: The present invention relates to a decoding device and method for a MIMO system. A linear process is applied to a received signal vector by using a channel matrix estimated from the received signal vector and a poly-diagonalized matrix, and a soft decision value is acquired through a trellis decode by using the linear process result. Since the linear preprocess is performed by using the poly-diagonalized matrix, it is possible to receive a MIMO signal having good packet error rate performance and less complexity. Also, since the tail-biting trellis decoding method is used based on the poly-diagonalized matrix that is generated by poly-diagonalizing the effective channel matrix during the process for eliminating the signal interference, the soft decision value for the symbol can be generated with a simple hardwired device and less operation complexity.

Abstract: An exemplary automatic gain control device includes: a radio frequency receiver for receiving a plurality of first signals through a plurality of antennas, respectively controlling gains of the plurality of first received signals, and outputting the plurality of the first signals having the controlled gain as a plurality of second signals; a signal saturation detecting unit for outputting a saturation index determination value when the number of plurality of second signals that are greater than a threshold value is greater than a predetermined number; and a gain controlling unit for comparing power values of the plurality of second signals to detect one power value, and outputting a gain value determined based on a detected power value and a saturation index determination value to the radio frequency receiver.

Abstract: There is provided to a method for encoding an LDPC (Low Density Parity Check) code using the result of checking a previously specified parity, including the steps of: forming a parity bit check matrix having a dual diagonal structure consisting of (N-K) rows for check nodes and (N-K) columns on the basis of the H matrix; calculating the values of all the parity bits by inserting a given binary value in sub-blocks, with the parity bit check matrix formed on the H matrix; if the values of the parity bits are incorrect, checking the parity bit corresponding to the sub-block located in the last part of the H matrix; searching the parity bit parts where the parity bit check result is represented as “1”; performing an XOR operation in sub-blocks on the parity bit part obtained through a simultaneous equation between the parity bits of the searched parity bit parts and the parity bit parts; and determining the value of the parity bit satisfying the condition that the value obtained by multiplying the H matrix by a c