Patents by Inventor Chan-Hong Chern

Chan-Hong Chern has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Circuit for reducing negative bias temperature instability
    Patent number: 9419617
    Abstract: A circuit comprises a control circuit having an output node. The circuit also comprises a half latch keeper circuit coupled to the control circuit. The half latch keeper circuit is configured to control the output node during a standby mode. The circuit also comprises a transistor coupled to the output node. The control circuit is configured to turn off the transistor during the standby mode.
    Type: Grant
    Filed: July 15, 2014
    Date of Patent: August 16, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chan-Hong Chern, Fu-Lung Hsueh, Ming-Chieh Huang, Bryan Sheffield, Chih-Chang Lin
  • Multi-stage transimpedance amplifier and a method of using the same
    Patent number: 9407218
    Abstract: A multi-stage transimpedance amplifier (TIA) which includes a common gate amplifier configured to receive a current signal, the common gate amplifier is configured to convert the current signal into an amplified voltage signal. The multi-stage TIA further includes a capacitive degeneration amplifier configured to receive the amplified voltage signal, the capacitive degeneration amplifier is configured to equalize the amplified voltage signal to form an equalized signal. The multi-stage TIA further includes an inverter configured to receive the equalized signal, the inverter is configured to increase a signal strength of the equalized signal to form an output signal. The multi-stage TIA further includes a feedback configured to receive the output signal, wherein the feedback is connected to an input and an output of the inverter.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: August 2, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Ching Huang, Chan-Hong Chern, Ming-Chieh Huang, Chih-Chang Lin
  • Capacitive load PLL with calibration loop
    Patent number: 9391626
    Abstract: A circuit includes a capacitive-load voltage controlled oscillator having an input configured to receive a first input signal and an output configured to output an oscillating output signal. A calibration circuit is coupled to the voltage controlled oscillator and is configured to output one or more control signals to the capacitive-load voltage controlled oscillator for adjusting a frequency of the oscillating output signal. The calibration circuit is configured to output the one or more control signals in response to a comparison of an input voltage to at least one reference voltage.
    Type: Grant
    Filed: August 11, 2014
    Date of Patent: July 12, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chan-Hong Chern, Tao Wen Chung, Ming-Chieh Huang, Chih-Chang Lin, Tsung-Ching Huang, Fu-Lung Hsueh
  • LEVEL SHIFTING CIRCUIT, APPARATUS AND METHOD OF OPERATING THE SAME
    Publication number: 20160173095
    Abstract: A level shifting circuit includes an input circuit, a leakage divider circuit, a skew inverter circuit and a buffering circuit. The input circuit has an input terminal configured to receive an input voltage. The input circuit is configured to receive a first voltage and a second voltage. The leakage divider circuit is configured to receive a third voltage. The leakage divider circuit is connected to the input circuit. The skew inverter circuit is configured to receive the third voltage. The skew inverter circuit is connected to the leakage divider circuit and the input circuit. The buffering circuit has a terminal configured to output an output voltage. The buffering circuit is connected to an output terminal of the skew inverter circuit. The level shifting circuit is free of capacitors.
    Type: Application
    Filed: February 22, 2016
    Publication date: June 16, 2016
    Inventors: Tsung-Ching (Jim) HUANG, Chan-Hong CHERN, Ming-Chieh HUANG, Chih-Chang LIN
  • Voltage supply circuit having an absorption unit and method for operating the same
    Patent number: 9360876
    Abstract: A voltage supply unit including a regulator unit, a voltage divider and a first current mirror. The regulator unit is configured to receive a first voltage signal and a second voltage signal, and is configured to generate a third voltage signal. The voltage divider is connected between the first current mirror and the regulator unit, and controls the second voltage signal. The first current mirror is connected to the regulator unit, an input voltage supply and the voltage divider. The first current mirror is configured to generate a first current signal and a second current signal, the second current signal is mirrored from the first current signal, the first current signal is controlled by the third voltage signal and the second current signal controls an output voltage supply signal.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: June 7, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chan-Hong Chern, Tsung-Ching Huang, Chih-Chang Lin, Ming-Chieh Huang, Fu-Lung Hsueh
  • METHOD OF OPERATING A VOLTAGE REGULATOR
    Publication number: 20160155488
    Abstract: A method of operating a first voltage regulator includes electrically coupling a transistor of an output stage of the first voltage regulator between a first power voltage and a second power voltage, and reverse biasing a bulk of the transistor by a back-bias circuit during a standby mode of a memory array. The first voltage regulator is coupled to a second voltage regulator and reverse biasing the bulk of the transistor reduces a contention current between the first voltage regulator and the second voltage regulator.
    Type: Application
    Filed: February 3, 2016
    Publication date: June 2, 2016
    Inventors: Ming-Chieh HUANG, Chan-Hong CHERN, Tien Chun YANG, Chih-Chang LIN, Yuwen SWEI
  • DELAY LINE CIRCUIT
    Publication number: 20160149564
    Abstract: A delay line circuit includes a plurality of delay units configured to receive an input signal and to provide a first output signal. The plurality of delay units is configured to selectively invert or relay the input signal to produce the first output signal based on a first instruction received from a delay line controller. A phase interpolator unit includes an offset unit configured to selectively add a speed control unit in the phase interpolator unit based on a second instruction received from the delay line controller. The phase interpolator unit is further configured to receive the first output signal and provide a second output signal.
    Type: Application
    Filed: November 26, 2014
    Publication date: May 26, 2016
    Inventors: Ming-Chieh HUANG, Chan-Hong CHERN, Tsung -Ching (Jim) HUANG, Chih-Chang LIN, Tien-Chun YANG
  • CURRENT GENERATOR AND METHOD OF OPERATING
    Publication number: 20160116930
    Abstract: A current generator includes an amplifier having a first terminal configured to receive a first voltage, a tunable resistance circuit coupled to an output terminal of the amplifier through a first transistor, a calibration circuit coupled to the tunable resistance circuit, and a second transistor. The second transistor includes a gate terminal coupled to the output terminal of the amplifier and a drain terminal coupled to a load. The calibration circuit is configured to adjust a resistance setting of the tunable resistance circuit.
    Type: Application
    Filed: January 6, 2016
    Publication date: April 28, 2016
    Inventors: Ming-Chieh Huang, Chan-Hong Chern, Chih-Chang Lin
  • Dummy Metal Gate Structures to Reduce Dishing During Chemical-Mechanical Polishing
    Publication number: 20160086949
    Abstract: The described embodiments of mechanisms for placing dummy gate structures next to and/or near a number of wide gate structures reduce dishing effect for gate structures during chemical-mechanical polishing of gate layers. The arrangements of dummy gate structures and the ranges of metal pattern density have been described. Wide gate structures, such as analog devices, can greatly benefit from the reduction of dishing effect.
    Type: Application
    Filed: December 4, 2015
    Publication date: March 24, 2016
    Inventors: Chan-Hong Chern, Chih-Chang Lin, Julie Tran, Jacklyn Chang
  • DECISION FEEDBACK EQUALIZER SUMMATION CIRCUIT
    Publication number: 20160087817
    Abstract: A circuit includes a summation circuit for receiving an input data signal and a feedback signal including a previous data bit. The summation circuit is configured to output a conditioned input data signal to a clock and data recovery circuit. A first flip-flop is coupled to an output of the summation circuit and is configured to receive a first set of bits of the conditioned input data signal and a first clock signal having a frequency that is less than a frequency at which the input data signal is received by the first summation circuit. A second flip-flop is coupled to the output of the summation circuit and is configured to receive a second set of bits of the conditioned input data signal and a second clock signal having a frequency that is less than the frequency at which the input data signal is received by the first summation circuit.
    Type: Application
    Filed: September 22, 2014
    Publication date: March 24, 2016
    Inventors: Ming-Chieh HUANG, Chan-Hong CHERN, Tao Wen CHUNG, Yuwen SWEI, Chih-Chang LIN, Tsung-Ching HUANG
  • Voltage regulator
    Patent number: 9293992
    Abstract: A voltage regulator circuit comprises an amplifier having an inverting input and a non-inverting input. The amplifier is configured to generate a control signal based on a reference signal at the inverting input of the amplifier and a feedback signal at the non-inverting input of the amplifier. The voltage regulator circuit also comprises an output node, a first power node, a second power node, and a driver that generates a driving current flowing toward the output node in response to the control signal. The driver is coupled between the first power node and the output node. A first transistor having a gate is coupled between the output node and the second power node. A bias circuit outside the amplifier supplies a bias signal to the gate of the first transistor, which is configured to operate in a saturation mode based on the bias signal supplied by the bias circuit.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: March 22, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chan-Hong Chern, Tzu Ching Chang, Min-Shueh Yuan, Yuwen Swei, Chih-Chang Lin, Chiang Pu, Ming-Chieh Huang, Kuoyuan Hsu
  • CHARGE PUMP INITIALIZATION DEVICE, INTEGRATED CIRCUIT HAVING CHARGE PUMP INITIALIZATION DEVICE, AND METHOD OF OPERATION
    Publication number: 20160079849
    Abstract: An initialization device for a charge pump includes a driving circuit and a bias voltage circuit. The driving circuit is between two power supply nodes. The driving circuit includes a first node configured to be coupled to an output electrode of a capacitor in the charge pump. The bias voltage circuit is coupled to the two power supply nodes. The bias voltage circuit includes a second node coupled to a control terminal of the driving circuit. In response to an applied initialization signal, the bias voltage circuit is configured to output a bias voltage to the second node. The bias voltage has at least two levels that correspond to levels of the applied initialization signal. In response to the bias voltage, the driving circuit is configured to output an output signal having at least two levels that correspond to the at least two levels of the bias voltage.
    Type: Application
    Filed: November 20, 2015
    Publication date: March 17, 2016
    Inventors: Chan-Hong CHERN, Chih-Chang LIN, Tsung-Ching HUANG, Ming-Chieh HUANG
  • CIRCUIT AND METHOD FOR INCREASING INDUCTOR CURRENT
    Publication number: 20160072279
    Abstract: A method of increasing a current flowing through an inductor includes receiving an input signal with a driver stage, the driver stage including the inductor coupled in series with a loading between an output node of the driver stage and a power line. In response to a transition in the input signal from a first voltage state to a second voltage state, a first current flowing through the loading and the inductor is increased. During the transition in the input signal, the current flowing through the inductor is increased by increasing a second current in a circuitry though a node between the inductor and the loading.
    Type: Application
    Filed: November 17, 2015
    Publication date: March 10, 2016
    Inventors: Tao Wen CHUNG, Chan-Hong CHERN, Ming-Chieh HUANG, Chih-Chang LIN, Yuwen SWEI
  • INPUT/OUTPUT CIRCUIT
    Publication number: 20160072502
    Abstract: A circuit includes a first power node, a second power node, an output node, a plurality of first transistors and a plurality of second transistors. The plurality of first transistors is serially coupled between the first power node and the output node. The plurality of second transistors is serially coupled between the second power node and the output node.
    Type: Application
    Filed: November 18, 2015
    Publication date: March 10, 2016
    Inventors: Chan-Hong CHERN, Tsung-Ching HUANG, Chih-Chang LIN, Ming-Chieh HUANG, Fu-Lung HSUEH
  • DELAY LINE CIRCUIT WITH VARIABLE DELAY LINE UNIT
    Publication number: 20160065194
    Abstract: A delay line circuit includes a plurality of delay circuits and a variable delay line circuit. The plurality of delay circuits receives an input signal and to generate a first output signal. The first output signal corresponds to a delayed input signal or an inverted input signal. The variable delay line circuit receives the first output signal. The variable delay line circuit includes an input end, an output end, a first and a second path. The input end is configured to receive the first output signal. The output end is configured to output a second output signal. The first path includes a first plurality of inverters and a first circuit. The second path includes a second plurality of inverters and a second circuit. The received first output signal is selectively transmitted through the first or second path based on a control signal received from a delay line controller.
    Type: Application
    Filed: November 12, 2015
    Publication date: March 3, 2016
    Inventors: Ming-Chieh HUANG, Chan-Hong CHERN, Tsung-Ching HUANG, Chih-Chang LIN, Fu-Lung HSUEH
  • Integrated circuits having dummy gate electrodes and methods of forming the same
    Patent number: 9275994
    Abstract: An integrated circuit comprises a gate electrode of at least one active transistor. The integrated circuit also comprises a first dummy gate electrode on a first side of the gate electrode. The integrated circuit further comprises a second dummy gate electrode on a second side of the gate electrode, the second side being opposite the first side. The integrated circuit additionally comprises a diffusion ring surrounding the gate electrode, the first dummy gate electrode, and the second dummy gate electrode. The integrated circuit also comprises a diffusion area extending from a first edge of the diffusion ring to a second edge of the diffusion ring.
    Type: Grant
    Filed: November 18, 2014
    Date of Patent: March 1, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Mei-Hui Huang, Chan-Hong Chern
  • Amplifier inductor sharing for inductive peaking and method therefor
    Patent number: 9276537
    Abstract: A method of sharing inductors for inductive peaking of an amplifier includes calculating a single stage inductance of a single stage for inductive peaking in order to have a stable impulse response. The method further includes determining a number of stages for shared inductance for inductive peaking. The method further includes sharing at least two inductors having the shared inductance among the determined number of stages for inductive peaking.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: March 1, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tao Wen Chung, Chan-Hong Chern, Ming-Chieh Huang, Chih-Chang Lin, Yuwen Swei
  • Voltage regulator
    Patent number: 9275719
    Abstract: A voltage regulator includes an amplifier, an output stage coupled with the amplifier, at least one back-bias circuit, and an output end coupled with the output stage and with the amplifier. The output stage includes at least one transistor having a bulk and a drain. The at least one back-bias circuit is coupled with the bulk of the at least one transistor. The output end is configured to be coupled with a memory array and with an output end of another voltage regulator. The back-bias circuit is configured to reduce a contention current between the voltage regulator and the other voltage regulator during a standby mode.
    Type: Grant
    Filed: April 28, 2015
    Date of Patent: March 1, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Chieh Huang, Chan-Hong Chern, Tien Chun Yang, Chih-Chang Lin, Yuwen Swei
  • Level shifting apparatus and method of using the same
    Patent number: 9270276
    Abstract: A level shifting apparatus includes a first capacitor, a first side of the first capacitor configured to receive a first voltage. The level shifting apparatus further includes an edge detector configured to receive the first voltage. The level shifting apparatus further includes an output inverter connected to a second side of the first capacitor, the output inverter configured to output an voltage-level shifted signal of the level shifting apparatus. The level shifting apparatus further includes a latch loop configured to receive feedback the output signal to an input of the output inverter, wherein the edge detector is configured to selectively interrupt feedback of the output signal to the input of the output inverter.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: February 23, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Ching (Jim) Huang, Chan-Hong Chern, Ming-Chieh Huang, Chih-Chang Lin
  • Integrated circuits including a charge pump circuit and operating methods thereof
    Patent number: RE46107
    Abstract: An integrated circuit includes a first current source. A second current source is electrically coupled with the first current source via a conductive line. A switch circuit is coupled between the first current source and the second current source. A first circuit is coupled between a first node and a second node. The first node is disposed between the first current source and the switch circuit. The second node is coupled with the first current source. The first circuit is configured for substantially equalizing voltages on the first node and the second node. A second circuit is coupled between a third node and a fourth node. The third node is disposed between the second current source and the switch circuit. The fourth node is disposed coupled with the second current source. The second circuit is configured for substantially equalizing voltages on the third node and the fourth node.
    Type: Grant
    Filed: May 21, 2014
    Date of Patent: August 16, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Steven Swei, Chih-Chang Lin, Tien-Chun Yang, Chan-Hong Chern, Ming-Chieh Huang