Abstract: A level shifting apparatus includes a first inverter configured to receive an input signal and a second inverter capacitively coupled with an output of the first inverter, the second inverter being configured to output an output signal. A transmission gate is configured to feed back the output signal to an input of the second inverter, wherein the transmission gate is configured to selectively interrupt feedback of the output signal to the input of the second inverter.

Abstract: A latch circuit includes a first input node, a second input node, a first output node, a second output node, a first switching device coupled between the first output node and the second output node, and a first amplification circuit coupled with the first input node, the second input node, the first output node, and the second output node. The first switching device is configured to be turned on in response to a first state of a clock signal and to be turned off in response to a second state of the clock signal. The first amplification circuit is configured to cause a voltage difference across the first switching device based on voltage levels of the first input node and the second input node in response to the first state of the clock signal.

Abstract: A semiconductor device includes a power transistor and a driving circuit. The driving circuit is coupled to and is configured to drive the power transistor and includes first and second stages. The second stage is coupled between the first stage and the power transistor. Each of the first and second stages includes a pair of enhancement-mode high-electron-mobility transistors (HEMTs). The construction as such lowers a static current of the driving circuit.

Abstract: A circuit includes a first circuit, a second circuit and a third circuit. The first circuit is configured to receive a first phase of a clock signal, a second phase of a clock signal and a first control signal. The first circuit is configured to generate a first interpolated phase of a clock signal. The second circuit is configured to receive a third phase of a clock signal, a fourth phase of a clock signal and a second control signal, and generate a second interpolated phase of a clock signal. The third circuit is configured to receive the first interpolated phase of the clock signal and the second interpolated phase of the clock signal, and generate the first control signal. The first control signal dynamically adjusts the first interpolated phase of the clock signal.

Abstract: An integrated circuit includes transistor and resistor. The transistor includes a gate stack. The gate stack includes a first dielectric layer, a first conductive layer over the first dielectric layer, a second conductive layer over the first conductive layer, and a second dielectric layer over the second conductive layer. The transistor also includes source/drain (S/D) regions adjacent to the gate stack. The resistor adjacent to the transistor, and includes a third dielectric layer.

Abstract: Semiconductor package structures and methods of forming the same are provided. An interposer is bonded to a printed circuit board (PCB) or package substrate through first solder bumps disposed on a first side of the interposer. The first solder bumps have a first pitch. A plurality of semiconductor chips are formed, and each of the semiconductor chips is bonded to a second side of the interposer through second solder bumps. The second solder bumps have a second pitch that is less than the first pitch. Each of the semiconductor chips includes a substrate with one or more transistors or integrated circuits formed thereon.

Abstract: Semiconductor structures including isolation regions and methods of forming the same are provided. A first layer is formed over a substrate, where the first layer comprises a semiconductor material. First and second trenches are etched, with each of the first and second trenches extending through the first layer and into the substrate. A wet etchant is introduced into the trenches, and the wet etchant etches a first opening below the first trench and a second opening below the second trench. Each of the first and second openings extends laterally below the first layer. The first and second openings are separated by a portion of the substrate adjoining the first and second openings. An oxidation process is performed to oxidize the portion of the substrate adjoining the first and second openings. An insulating material is deposited that fills the openings and the trenches.

Abstract: A level shifting circuit includes an input circuit, a leakage divider circuit, a skew inverter circuit and a buffering circuit. The input circuit has an input terminal configured to receive an input voltage. The input circuit is configured to receive a first voltage and a second voltage. The leakage divider circuit is configured to receive a third voltage. The leakage divider circuit is connected to the input circuit. The skew inverter circuit is configured to receive the third voltage. The skew inverter circuit is connected to the leakage divider circuit and the input circuit. The buffering circuit has a terminal configured to output an output voltage. The buffering circuit is connected to an output terminal of the skew inverter circuit. The level shifting circuit is free of capacitors.

Abstract: A voltage supply unit includes a regulator unit, a current mirror, and a cascode unit. The regulator unit is configured to receive first and second voltage signals and generate a third voltage signal. The current mirror is configured to generate first and second current signals based on the third voltage signal. The cascode unit includes a first terminal configured to receive the first current signal, a second terminal configured to receive a first bias voltage signal, a third terminal configured to receive a second bias voltage signal, and a fourth terminal electrically connected to the regulator unit. An output voltage supply signal is controlled by the second current signal.

Abstract: In one embodiment, a method of fabricating a semiconductor device having an isolated first transistor circuit and an isolated second transistor circuit is provided. The method comprises providing a silicon on insulator (SOI) wafer and fabricating an isolated first silicon region and an isolated second silicon region on the SOI wafer wherein each of the first silicon region and the second silicon region is bounded on its sides by a trench filled with insulator material. The method further comprises fabricating an active area comprising GaN on each of the first silicon region and the second silicon region to form the first transistor circuit and the second transistor circuit and fabricating source, drain, gate, and body connections for each of the first transistor circuit and the second transistor circuit.

Abstract: A method of increasing a current flowing through an inductor includes receiving an input signal with a driver stage, the driver stage including the inductor coupled in series with a loading between an output node of the driver stage and a power line. In response to a transition in the input signal from a first voltage state to a second voltage state, a first current flowing through the loading and the inductor is increased. During the transition in the input signal, the current flowing through the inductor is increased by increasing a second current in a circuitry though a node between the inductor and the loading.

Abstract: A circuit includes a summation circuit for receiving an input data signal and a feedback signal including a previous data bit. The summation circuit is configured to output a conditioned input data signal to a clock and data recovery circuit. A first flip-flop is coupled to an output of the summation circuit and is configured to receive a first set of bits of the conditioned input data signal and a first clock signal having a frequency that is less than a frequency at which the input data signal is received by the first summation circuit. A second flip-flop is coupled to the output of the summation circuit and is configured to receive a second set of bits of the conditioned input data signal and a second clock signal having a frequency that is less than the frequency at which the input data signal is received by the first summation circuit.

Abstract: A delay line circuit includes a plurality of delay circuits and a variable delay line circuit. The plurality of delay circuits receives an input signal and to generate a first output signal. The first output signal corresponds to a delayed input signal or an inverted input signal. The variable delay line circuit receives the first output signal. The variable delay line circuit includes an input end, an output end, a first and a second path. The input end is configured to receive the first output signal. The output end is configured to output a second output signal. The first path includes a first plurality of inverters and a first circuit. The second path includes a second plurality of inverters and a second circuit. The received first output signal is selectively transmitted through the first or second path based on a control signal received from a delay line controller.

Abstract: A delay line circuit includes: a coarse-tuning arrangement, including delay units; and a fine-tuning arrangement including at least three serially-connected inverters. The coarse-tuning arrangement is configured to receive an input signal and coarsely-tune the input signal, the coarsely-tuning including transferring the input signal through a selected number of the delay units and thereby producing a first output signal. The fine-tuning arrangement is configured to receive the first output signal, finely-tune the first output signal, and produce a second output signal, the finely-tuning including selectively connecting a speed control unit to a node between a corresponding pair of the at least three serially-connected inverters.

Abstract: A circuit includes an output node, a set of first transistors, a set of second transistors, and a first and second power node. The first power node is configured to carry a first voltage level, and second power node is configured to carry a second voltage level. Set of first transistors is coupled between the first power node and output node. Set of second transistors is coupled between the second power node and output node. The first control signal generating circuit is coupled to a gate of a first transistor of the set of first transistors and a gate of a first transistor of the set of second transistors. The first control signal generating circuit is configured to generate a set of biasing signals for the gate of the first transistor of the set of first transistors and the gate of the first transistor of the set of second transistors.

Abstract: The described embodiments of mechanisms for placing dummy gate structures next to and/or near a number of wide gate structures reduce dishing effect for gate structures during chemical-mechanical polishing of gate layers. The arrangements of dummy gate structures and the ranges of metal pattern density have been described. Wide gate structures, such as analog devices, can greatly benefit from the reduction of dishing effect.

Abstract: A method of forming an integrated circuit. The method includes forming at least one transistor and at least one electrical fuse over a substrate. Forming the at least one transistor includes forming a gate dielectric structure over a substrate and a work-function metallic layer over the gate dielectric structure. Forming the at least one transistor further includes forming a conductive layer over the work-function metallic layer and a source/drain (S/D) region being disposed adjacent to each sidewall of the gate dielectric structure. Forming the at least one transistor further includes forming a diffusion barrier layer between the gate dielectric structure and the work-function layer. Forming the at least one electrical fuse includes forming a first semiconductor layer over the substrate. Forming the at least one electrical fuse includes forming a first silicide layer on the first semiconductor layer, wherein the diffusion barrier layer is formed before the first silicide layer.

Abstract: A delay line circuit includes a plurality of delay units configured to receive an input signal and to provide a first output signal. The plurality of delay units is configured to selectively invert or relay the input signal to produce the first output signal based on a first instruction received from a delay line controller. A phase interpolator unit includes an offset unit configured to selectively add a speed control unit in the phase interpolator unit based on a second instruction received from the delay line controller. The phase interpolator unit is further configured to receive the first output signal and provide a second output signal.

Abstract: An initialization device for a charge pump includes a driving circuit and a bias voltage circuit. The driving circuit is between two power supply nodes. The driving circuit includes a first node configured to be coupled to an output electrode of a capacitor in the charge pump. The bias voltage circuit is coupled to the two power supply nodes. The bias voltage circuit includes a second node coupled to a control terminal of the driving circuit. In response to an applied initialization signal, the bias voltage circuit is configured to output a bias voltage to the second node. The bias voltage has at least two levels that correspond to levels of the applied initialization signal. In response to the bias voltage, the driving circuit is configured to output an output signal having at least two levels that correspond to the at least two levels of the bias voltage.

Abstract: Some embodiments regard a circuit comprising: a first circuit configured to lock a frequency of an output clock to a frequency of a reference clock; a second circuit configured to align an input signal to a phase clock of the output clock; a third circuit configured to use a first set of phase clocks of the output clock and a second set of phase clocks of the output clock to improve alignment of the input signal to the phase clock of the output clock; and a lock detection circuit configured to turn on the first circuit when the frequency of the output clock is not locked to the frequency of the reference clock; and to turn off the first circuit and to turn on the second circuit and the third circuit when the frequency of the output clock is locked to the frequency of the reference clock.