Abstract: In one embodiment, the apparatus includes a driver circuit configured such that for each symbol in a set of possible symbols, the driver circuit generates at least one data signal at an associated voltage level. Here, adjacent voltage levels defme an associated voltage interval, and the driver circuit is configured to generate the voltage levels such that a central voltage interval is less than at least one of the voltage intervals adjacent to the central voltage interval.

Abstract: In the example embodiments, test signals sent from a transmitting system are received at a receiving system. The receiving system generates a determination signal indicating, in one embodiment, whether received signals have a desired relationship with respect to a clock signal at the receiving system. Timing of the clock signal or timing for transmitting signals may be adjusted based on the determination. In another embodiment, the receiving system generates a determination signal indicating whether the pulse width of a lone pulse signal equals a desired time interval. Equalization or pre-emphasis is controlled based on the determination signal.

Abstract: A clock generating apparatus includes a clock generator and a controllable delay line. The clock generator receives an external clock signal and generates multiple clock signals having different phases by delaying the external clock signal. The controllable delay line receives one of the multiple clock signals as a first clock signal and delays the first clock signal by a first interval in response to an externally applied control signal. The delayed first clock signal is input to the clock generator.

Abstract: An output driver includes a pull-up unit including a pull-up element and a first inductive peaking element connected in series between a first voltage and an output node and a pull-down unit including a pull-down element and a second inductive peaking element connected in series between a second voltage and the output node. The pull-up and pull-down elements receive an input data signal and adjust a voltage level of the output node, and the first and second inductive peaking elements perform an inductive peaking operation when the input data signal transitions.

Abstract: A stress detection circuit includes a function block and a detection signal generation circuit. The function block outputs a first voltage such that the first voltage is varied depending on an extent that the function block is stressed. The detection signal generation circuit generates a stress detection signal based on the first voltage and a second voltage during a test mode. The stress detection signal represents integration of the function block, and a level of the second voltage corresponds to a level of the first voltage before the function block is stressed.

Abstract: A communication system using multi-phase clock signals. The communication system includes a transmitter and a receiver. The transmitter outputs first data and a clock signal based on first multi-phase clock signals, and performs a coarse lock operation on the clock signal in response to a bit lock detection signal indicating whether or not the first data are bit-locked. The receiver receives the first data and the clock signal from the transmitter, generates second multi-phase clock signals based on the clock signal, generates second data by sampling the first data based on the second multi-phase clock signals, and performs a fine lock operation on the second multi-phase clock signals in response to the bit lock detection signal. Therefore, a jitter noise may be reduced and a size of a multi-phase clock generator included in the receiver may be reduced.

Abstract: In a semiconductor device and method for decreasing noise of an output driver block, the semiconductor device monitors differentially amplified voltages output from an output driver block and controls a voltage level at a cross-over point between the differentially amplified voltages so that noise that may be caused by reactance occurring in the output driver block can be removed and so that inter-symbol interference (ISI) that may be caused when a voltage level of a serialized input data is interfered with a voltage level of previously input data can be prevented.

Abstract: Phase correction circuits and methods for reducing phase skew between multiphase clock signals and a semiconductor device including the circuit are provided. The semiconductor device includes a phase correction circuit and an output buffer. The phase correction circuit corrects phase skew between multiphase clock signals and generates skew-corrected clock signals. The output buffer outputs data in synchronization with the skew-corrected clock signals. The phase correction circuit includes a phase corrector, a replication output buffer, a phase detector, and a controller. The phase corrector corrects a duty cycle of a first clock signal, a duty cycle of a second clock signal, and phase skew between the first and second clock signals and generates skew-corrected first and second clock signals. The replication output buffer has the same structure as a data output buffer and outputs replication data in synchronization with the skew-corrected first and second clock signals.

Abstract: A bubble error rejecter includes a cascade of front and rear voting sections for correcting bubble errors spanning multiple bits from interpolation. The front voting section generates first correction codes from first thermometer codes determined from preamplified signals. The rear voting section generates second correction codes from the first correction codes and second thermometer codes determined from interpolation of the preamplified signals.

Abstract: A semiconductor device, a method related to the semiconductor device, and a printed circuit board are disclosed. The semiconductor device includes a chip, a package including a plurality of power voltage terminals and a plurality of ground voltage terminals, wherein the chip is disposed in the package. The semiconductor device further includes an impedance circuit connected between a DC component power voltage terminal and a ground voltage, wherein the DC component power voltage terminal is one of the plurality of power voltage terminals, and an AC component interrupter connected between the DC component power voltage terminal and a power voltage. Both the AC component and a DC component of the power voltage are applied to each of the power voltage terminals except the DC component second power voltage terminal, and the ground voltage is applied to each of the ground voltage terminals.

Abstract: A preamplifier circuit includes a differential amplifying unit, an offset detection unit and a reference signal generation unit. The differential amplifying unit compares an input signal pair with a reference signal pair to generate an output signal pair. The offset detection unit detects an offset of the output signal pair received from the differential amplifying unit to generate a calibration signal in an offset calibration mode. The reference signal generation unit adjusts the reference signal pair based on the calibration signal, and the reference signal pair is fed-back to the differential amplifying unit.

Abstract: Disclosed is a novel high 1,4-cis polybutadiene-polyurethane copolymer and a preparation method thereof. The present invention provides a high 1,4-cis polybutadiene-polyurethane copolymer represented by the following formula 1 and having an average molecular weight of at least 100,000, and a method for preparing the high 1,4-cis polybutadiene-polyurethane copolymer that includes polymerizing 1,3-butadiene or butadiene derivatives with a catalyst comprising a rare earth compound, a halogen-containing compound and an organoaluminum compound in the presence of a non-polar solvent, to prepare a polybutadiene having a high 1,4-cis content of at least 95%; and then introducing a polyurethane group to the polybutadiene.

Abstract: A transmission system and method may be provided. The transmission system may transmit 2-bit data for each transmission line set and each transmission line set may include first, second and/or third transmission lines arranged in order. The first, second and/or third transmission lines may respectively transmit first, second and/or third signals each having one of first, second and/or third values such that a combination of a first electric field between the first and second transmission lines and a second electric field between the second and third transmission lines may be made depending on a logic state of the 2-bit data. The transmission system may transmit differential signals using a smaller number of transmission lines and the transmission system may transmit a larger number of signals in the same circuit area.

Abstract: An output driver includes a pull-up unit including a pull-up element and a first inductive peaking element connected in series between a first voltage and an output node and a pull-down unit including a pull-down element and a second inductive peaking element connected in series between a second voltage and the output node. The pull-up and pull-down elements receive an input data signal and adjust a voltage level of the output node, and the first and second inductive peaking elements perform an inductive peaking operation when the input data signal transitions.

Abstract: The present invention relates to a refrigerator. In the present invention, a communication pad 60 is installed in one of the doors 51 and 53 for opening and closing storage spaces formed in a refrigerator main body 50. The communication pad 60 is detachably installed in a seating; space 58 of the door 53. While an upper end of the communication pad 60 is seated in the seating space 58 by an upper clamp 61, a lower end of the communication pad 60 is seated in the seating space 58 by a lower clamp 61?. The upper clamp 61 and the lower clamp 61? are installed in the seating space 58 through hinge assemblies 65. Here, the hinge assemblies 65 are configured so that the upper and lower clamps 61 and 61? rotate only by a force of a predetermined value or higher. According to the present invention constructed as above, it is possible to get advantages in that the communication pad 60 is securely mounted to and easily dismounted from the door 53.

Abstract: A bubble error rejecter includes a cascade of front and rear voting sections for correcting bubble errors spanning multiple bits from interpolation. The front voting section generates first correction codes from first thermometer codes determined from preamplified signals. The rear voting section generates second correction codes from the first correction codes and second thermometer codes determined from interpolation of the preamplified signals.

Abstract: The present invention relates to a method for preparing homo- and co-polymers having high molecular weights in high yields by polymerizing cyclic olefin compounds using a complex prepared by mixing a nickel salt compound, an organoaluminoxane compound, and at least one organic boron compound.

Abstract: Disclosed herein is a flyback converter with a synchronous rectifier which is applied to a power supply of a portable computer such as a notebook PC. The flyback converter is operated in a critical conduction mode to turn on/off a main switch at a zero crossing point of an output voltage. The flyback converter is also adapted to supply a driving voltage to a synchronous switch using the output voltage. Therefore, there is no need for a secondary auxiliary coil of a transformer and for a Schottky diode to be connected in parallel with the synchronous switch, resulting in simplification in circuit design.

Abstract: The present invention provides a method for preparing homo- and co-polymers by polymerizing cyclic olefin compounds using addition polymerization. The method can produce a cyclic olefin polymer having a high molecular weight with a high yield in the presence of, as an addition polymerization catalyst, a complex prepared by mixing a nickel salt compound and an organoaluminoxane compound with at least one fluorine-containing aromatic hydrocarbon compound represented by the following formula 1 or 2 as a catalyst activator: C6RmH6-mFormula 1 where R is CF3; and m is from 1 to 3, or C6FnH6-nFormula 2 where n is from 1 to 6.

Abstract: Disclosed herein is a variable-frequency flyback.