Abstract: Provided are a semiconductor device and a method of forming the semiconductor device. The semiconductor device includes an active region of which an edge is curved. The semiconductor device includes a gate insulating layer, a floating gate, a gate interlayer dielectric layer and a control gate line on the active region. The semiconductor device includes an oxide pattern having a concave top surface between adjacent floating gates. The control gate may be sufficiently spaced apart from the active region by the oxide pattern. The method can provide a semiconductor device that includes a reoxidation process, an active region having a curved edge and an oxide pattern having a top surface of a curved concave shape.

Abstract: Provided are a semiconductor device and a method of forming the semiconductor device. The semiconductor device includes an active region of which an edge is curved. The semiconductor device includes a gate insulating layer, a floating gate, a gate interlayer dielectric layer and a control gate line on the active region. The semiconductor device includes an oxide pattern having a concave top surface between adjacent floating gates. The control gate may be sufficiently spaced apart from the active region by the oxide pattern. The method can provide a semiconductor device that includes a reoxidation process, an active region having a curved edge and an oxide pattern having a top surface of a curved concave shape.

Abstract: Provided are a semiconductor device and a method of forming the semiconductor device. The semiconductor device includes an active region of which an edge is curved. The semiconductor device includes a gate insulating layer, a floating gate, a gate interlayer dielectric layer and a control gate line on the active region. The semiconductor device includes an oxide pattern having a concave top surface between adjacent floating gates. The control gate may be sufficiently spaced apart from the active region by the oxide pattern. The method can provide a semiconductor device that includes a reoxidation process, an active region having a curved edge and an oxide pattern having a top surface of a curved concave shape.

Abstract: Semiconductor devices including a plurality of semiconductor layers. A plurality of transistors are on each of the semiconductor layers. The transistors include gate lines and have source regions and drain regions formed between the gate lines in the respective semiconductor layer including the transistors. The semiconductor devices further include a plurality of local source line structures. Each of the local source line structures is positioned on a corresponding one of the semiconductor layers and connects a plurality of the source regions formed on the corresponding one of the semiconductor layers. Methods of forming the semiconductor devices are also provided.

Abstract: A method of fabricating a nonvolatile memory device includes preparing a semiconductor substrate including a cell array region. The method also includes forming a recessed region in the cell array region by etching the semiconductor substrate. The method includes etching at least a portion of the semiconductor substrate that partially includes the recessed region and forming first and second trenches that differ in depth, intersect the recessed region, and link with each other. The method includes forming a device isolation layer having rugged bottoms and defining an active region by filling an insulating material in the first and second trenches. The method includes forming a gate insulation layer on the semiconductor substrate of the active region including the recessed region and forming a gate structure on the gate insulation layer, to fill the recessed region, the gate structure including a floating gate, an intergate insulating pattern, and a control gate.

Abstract: A method of fabricating a nonvolatile memory device includes preparing a semiconductor substrate including a cell array region. The method also includes forming a recessed region in the cell array region by etching the semiconductor substrate. The method includes etching at least a portion of the semiconductor substrate that partially includes the recessed region and forming first and second trenches that differ in depth, intersect the recessed region, and link with each other. The method includes forming a device isolation layer having rugged bottoms and defining an active region by filling an insulating material in the first and second trenches. The method includes forming a gate insulation layer on the semiconductor substrate of the active region including the recessed region and forming a gate structure on the gate insulation layer, to fill the recessed region, the gate structure including a floating gate, an intergate insulating pattern, and a control gate.

Abstract: Provided are a semiconductor device and a method of forming the semiconductor device. The semiconductor device includes an active region of which an edge is curved. The semiconductor device includes a gate insulating layer, a floating gate, a gate interlayer dielectric layer and a control gate line on the active region. The semiconductor device includes an oxide pattern having a concave top surface between adjacent floating gates. The control gate may be sufficiently spaced apart from the active region by the oxide pattern. The method can provide a semiconductor device that includes a reoxidation process, an active region having a curved edge and an oxide pattern having a top surface of a curved concave shape.

Abstract: A method of operating a non-volatile memory device is disclosed. The memory cell includes a channel region separating a source region and a drain region, a tunnel insulating layer, a charge storage layer, and a gate electrode formed over the channel region. The method includes applying a negative voltage to the gate electrode and applying a positive voltage to at least one of the source and drain regions to inject holes into the tunnel insulating layer and thereby remove electrons trapped in the tunnel insulating layer.

Abstract: A method of forming a contactless nonvolatile memory device includes preparing a semiconductor substrate including a cell array region, forming a plurality of mask patterns being parallel to each other on the semiconductor substrate in the cell array region, etching the semiconductor substrate using the mask patterns as an etch mask to form a plurality of recess regions, forming a gate insulating layer on sidewalls and bottoms of the recess regions, forming a floating gate layer on an upper surface of the semiconductor substrate to fill the recess regions, planarizing the floating gate layer to expose upper surfaces of the mask patterns and to form floating gate patterns in the recess regions, forming buried impurity diffusion regions in the semiconductor substrate under the mask patterns, forming an intergate dielectric layer, forming a control gate layer, and patterning the control gate layer, the intergate dielectric layer and the floating gate pattern to form a plurality of parallel word lines crossing th

Abstract: Semiconductor devices including a plurality of semiconductor layers. A plurality of transistors are on each of the semiconductor layers. The transistors include gate lines and have source regions and drain regions formed between the gate lines in the respective semiconductor layer including the transistors. The semiconductor devices further include a plurality of local source line structures. Each of the local source line structures is positioned on a corresponding one of the semiconductor layers and connects a plurality of the source regions formed on the corresponding one of the semiconductor layers. Methods of forming the semiconductor devices are also provided.

Abstract: A method of fabricating a nonvolatile memory device includes preparing a semiconductor substrate including a cell array region. The method also includes forming a recessed region in the cell array region by etching the semiconductor substrate. The method includes etching at least a portion of the semiconductor substrate that partially includes the recessed region and forming first and second trenches that differ in depth, intersect the recessed region, and link with each other. The method includes forming a device isolation layer having rugged bottoms and defining an active region by filling an insulating material in the first and second trenches. The method includes forming a gate insulation layer on the semiconductor substrate of the active region including the recessed region and forming a gate structure on the gate insulation layer, to fill the recessed region, the gate structure including a floating gate, an intergate insulating pattern, and a control gate.

Abstract: A method of forming a contactless nonvolatile memory device includes preparing a semiconductor substrate including a cell array region, forming a plurality of mask patterns being parallel to each other on the semiconductor substrate in the cell array region, etching the semiconductor substrate using the mask patterns as an etch mask to form a plurality of recess regions, forming a gate insulating layer on sidewalls and bottoms of the recess regions, forming a floating gate layer on an upper surface of the semiconductor substrate to fill the recess regions, planarizing the floating gate layer to expose upper surfaces of the mask patterns and to form floating gate patterns in the recess regions, forming buried impurity diffusion regions in the semiconductor substrate under the mask patterns, forming an intergate dielectric layer, forming a control gate layer, and patterning the control gate layer, the intergate dielectric layer and the floating gate pattern to form a plurality of parallel word lines crossing th

Abstract: A cell array of a flash memory device includes extended source strapping regions. The cell array includes a device isolation layer and active regions. The device isolation layer is formed in a semiconductor substrate, and the active regions are defined by the device isolation layer. Word lines cross over the active regions, and a common source line electrically connects the active regions between two word lines of word line pairs. A source strapping region is defined between the two word lines of the word line pairs. The source strapping region crosses multiple active regions.

Abstract: A cell array of a flash memory device includes extended source strapping regions. The cell array includes a device isolation layer and active regions. The device isolation layer is formed in a semiconductor substrate, and the active regions are defined by the device isolation layer. Word lines cross over the active regions, and a common source line electrically connects the active regions between two word lines of word line pairs. A source strapping region is defined between the two word lines of the word line pairs. The source strapping region crosses multiple active regions.

Abstract: A semiconductor device and a method for fabricating the same, wherein a thick side wall oxide film or polysilicon film is formed on the edge portion of the second silicon substrate. At the side wall of the oxide film or polysilicon film, the thickness of an active semiconductor substrate at its edge portion increases, thereby obtaining an increased threshold voltage at the edge portion. That is, the formation of the side wall oxide film is carried out to prevent a gate oxide film of the semiconductor device from being directly formed on each side wall of the active silicon substrate. As a result, it is possible to prevent a degradation in electrical characteristic due to a degradation in threshold voltage caused by a reduced thickness of the active semiconductor substrate at its edge portion.

Abstract: The present invention provide a method for forming a triple well. The triple well includes an n-well, a first p-well surrounded with the n-well and a second p-well apart from the first p-well and adjacent to the n-well. According to the present invention, only one conductivity type of impurities are implanted in each well. Therefore, it is possible to prevent the decrease of the carrier mobility and increase of the leakage current.

Abstract: A semiconductor device and a method for fabricating the same, wherein a thick side wall oxide film or polysilicon film is formed on the edge portion of the second silicon substrate. At the side wall of the oxide film or polysilicon film, the thickness of an active semiconductor substrate at its edge portion increases, thereby obtaining an increased threshold voltage at the edge portion. That is, the formation of the side wall oxide film is carried out to prevent a gate oxide film of the semiconductor device from being directly formed on each side wall of the active silicon substrate. As a result, it is possible to prevent a degradation in electrical characteristic due to a degradation in threshold voltage caused by a reduced thickness of the active semiconductor substrate at its edge portion.

Abstract: A semiconductor device having a silicon-on-insulator structure, and a method for fabricating the semiconductor device, wherein a thick silicon oxide film is formed on each side wall of an active silicon substrate, thereby obtaining an increased threshold voltage at the edge of the active silicon substrate. The semiconductor device includes a first silicon substrate, a first silicon oxide film formed over the first silicon substrate, a second silicon substrate on the first silicon oxide film, second silicon oxide films, respectively disposed on opposite side walls of the second silicon substrate, a gate oxide film formed on the second silicon substrate, a gate electrode formed over the gate oxide film, and source/drain impurity diffusion regions, respectively formed in portions of the second silicon substrate disposed at both sides of the gate electrode.

Abstract: A sense amplifier comprising a data refresh amplifier for supplying voltages to true and complementary bit lines in response to a first control signal to amplify true and complementary data on the true and complementary bit lines, respectively, a first transistor for amplifying current of the true data on the true bit line in response to a second control signal and transferring the amplified true data to a true input/output line, a second transistor for amplifying current of the complementary data on the complementary bit line in response to the second control signal and transferring the amplified complementary data to a complementary input/output line, a first switch for selectively forming a current path between the true input/output line and the true bit line, and a second switch for selectively forming a current path between the complementary input/output line and the complementary bit line.

Abstract: A fully planarized concave transistor is produced having a structure, wherein a lightly doped drain(LDD) region and a source/drain region are formed and accumulated on a semiconductor substrate in a predetermined pattern, a thick insulating layer is formed on the surface and the sidewall of the source/drain, a gate formed between the source and drain, with a gate insulating layer is formed between the source and the gate, and between the drain and the gate to insulate therebetween.