Abstract: A fully planarized concave transistor is produced having a structure, wherein a lightly doped drain(LDD) region and a source/drain region are formed and accumulated on a semiconductor substrate in a predetermined pattern, a thick insulating layer is formed on the surface and the sidewall of the source/drain, a gate formed between the source and drain, with a gate insulating layer is formed between the source and the gate, and between the drain and the gate to insulate therebetween.

Abstract: A method for forming contact holes in a semiconductor device, involving formation of a ring-shaped pad at a contact region. The ring-shaped pad is used as an etch barrier film upon forming a contact hole. The use of such a ring-shaped pad enables easy formation of a contact hole with a critical dimension. In accordance with this method, it is possible to increase a process margin upon the formation of contact holes for providing contacts with a critical dimension while maintaining an insulation between neighboring conductors.

Abstract: A sense amplifier comprising a data refresh amplifier for supplying voltages to true and complementary bit lines in response to a first control signal to amplify true and complementary data on the true and complementary bit lines, respectively, a first transistor fox amplifying current of the true data on the true bit line in response to a second control signal and transferring the amplified true data to a true input/output line, a second transistor for amplifying current of the complementary data on the complementary bit line in response to the second control signal and transferring the amplified complementary data to a complementary input/output line, a first switch for selectively forming a current path between the true input/output line and the true bit line, and a second switch for selectively forming a current path between the complementary input/output line and the complementary bit line.

Abstract: A method of manufacturing a semiconductor device, capable of securing an alignment margin between bit lines and a storage node contact is disclosed herein.