Patents by Inventor Chan-kyung Kim
Chan-kyung Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11917875Abstract: A display device includes a substrate including an active area having pixels and a non-active area including a pad region. A pad electrode is disposed in the pad region and includes a first pad electrode and a second pad electrode disposed on the first pad electrode. A first insulating pattern is interposed between the first and second pad electrodes. In a plan view, the first insulating pattern is positioned inside the first pad electrode, and a portion of the second pad electrode overlapping the first insulating pattern protrudes further from the substrate in a thickness direction than a portion of the second pad electrode not overlapping the first insulating pattern. The second pad electrode directly contacts a portion of the upper surface of the first pad electrode. In a plan view, an area of the second pad electrode is greater than an area of the first pad electrode.Type: GrantFiled: December 29, 2021Date of Patent: February 27, 2024Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Ki Kyung Youk, Chan Jae Park, Min Soo Kim, Yoon A Kim, Sang Duk Lee, Chel Gou Lim
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Patent number: 11889703Abstract: A magnetic junction memory device is provided. The magnetic junction memory device including a sensing circuit including a sensing node, the sensing node being connected to a first end of a transistor and configured to change a voltage of the sensing node in accordance with a resistance of a magnetic junction memory cell, a gating voltage generator circuit configured to generate a gating voltage of the transistor using a reference resistor and a reference voltage, and a read circuit configured to read data from the magnetic junction memory cell using the reference voltage and the voltage of the sensing node.Type: GrantFiled: October 27, 2022Date of Patent: January 30, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chan Kyung Kim, Eun Ji Lee, Ji Yean Kim, Tae Seong Kim, Jae Wook Joo
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Patent number: 11798621Abstract: A resistive memory device includes a resistive memory cell, a source line connected to one end of the resistive memory cell, a bit line connected to another end of the resistive memory cell, and a sensing circuit connected to the source line and the bit line. The sensing circuit is configured to generate a pull-up signal that is pulled up from a first voltage level to a second voltage level, based on a read current flowing through the resistive memory cell, generate a pull-down signal that is pulled down from a third voltage level to a fourth voltage level, based on the read current, and determine data that is stored in the resistive memory cell, based on a difference between the generated pull-up signal and the generated pull-down signal.Type: GrantFiled: March 26, 2021Date of Patent: October 24, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Chan Kyung Kim
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Patent number: 11651201Abstract: Provided is a memory device that includes a memory bank including a plurality of memory cells arranged in a region where a plurality of word lines and a plurality of bit lines of the memory device intersect each other, a sense amplifier configured to amplify a signal transmitted through selected bit lines among the plurality of bit lines, and an arithmetic circuit configured to receive a first operand from the sense amplifier, receive a second operand from outside the memory device, and perform an arithmetic operation by using the first operand and the second operand, based on an internal arithmetic control signal generated in the memory device.Type: GrantFiled: July 26, 2019Date of Patent: May 16, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chan-Kyung Kim, Soon-Young Kim, Jin-Min Kim, Jae-Hong Min, Sang-Kil Lee, Young-Nam Hwang
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Publication number: 20230051494Abstract: A magnetic junction memory device is provided. The magnetic junction memory device including a sensing circuit including a sensing node, the sensing node being connected to a first end of a transistor and configured to change a voltage of the sensing node in accordance with a resistance of a magnetic junction memory cell, a gating voltage generator circuit configured to generate a gating voltage of the transistor using a reference resistor and a reference voltage, and a read circuit configured to read data from the magnetic junction memory cell using the reference voltage and the voltage of the sensing node.Type: ApplicationFiled: October 27, 2022Publication date: February 16, 2023Applicant: Samsung Electronics Co., Ltd.Inventors: Chan Kyung KIM, Eun Ji LEE, Ji Yean KIM, Tae Seong KIM, Jae Wook JOO
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Patent number: 11515357Abstract: A magnetic junction memory device is provided. The magnetic junction memory device including a sensing circuit including a sensing node, the sensing node being connected to a first end of a transistor and configured to change a voltage of the sensing node in accordance with a resistance of a magnetic junction memory cell, a gating voltage generator circuit configured to generate a gating voltage of the transistor using a reference resistor and a reference voltage, and a read circuit configured to read data from the magnetic junction memory cell using the reference voltage and the voltage of the sensing node.Type: GrantFiled: February 24, 2020Date of Patent: November 29, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chan Kyung Kim, Eun Ji Lee, Ji Yean Kim, Tae Seong Kim, Jae Wook Joo
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Publication number: 20220375505Abstract: Magnetic junction memory devices and methods for writing data to memory devices are provided. The magnetic junction memory device includes a first memory bank including first magnetic junction memory cells, a first local write driver adjacent to the first memory bank, connected to global data lines, the first local write driver configured to write data to the first magnetic junction memory cells via local data lines, a second memory bank adjacent to the first memory bank and including second magnetic junction memory cells, a second local write driver adjacent to the second memory bank, connected to the global data lines, the second local write driver configured to write data to the second magnetic junction memory cells via local data lines, and a global write driver configured to provide first and second write data to the first and second local write driver, respectively, via the global data lines.Type: ApplicationFiled: August 8, 2022Publication date: November 24, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Chan Kyung KIM, Ji Yean KIM, Hyun Taek JUNG, Ji Eun KIM, Tae Seong KIM, Sang-Hoon JUNG, Jae Wook JOO
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Patent number: 11443791Abstract: Magnetic junction memory devices and methods for writing data to memory devices are provided. The magnetic junction memory device includes a first memory bank including first magnetic junction memory cells, a first local write driver adjacent to the first memory bank, connected to global data lines, the first local write driver configured to write data to the first magnetic junction memory cells via local data lines, a second memory bank adjacent to the first memory bank and including second magnetic junction memory cells, a second local write driver adjacent to the second memory bank, connected to the global data lines, the second local write driver configured to write data to the second magnetic junction memory cells via local data lines, and a global write driver configured to provide first and second write data to the first and second local write driver, respectively, via the global data lines.Type: GrantFiled: April 14, 2020Date of Patent: September 13, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chan Kyung Kim, Ji Yean Kim, Hyun Taek Jung, Ji Eun Kim, Tae Seong Kim, Sang-Hoon Jung, Jae Wook Joo
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Publication number: 20220076742Abstract: A resistive memory device includes a resistive memory cell, a source line connected to one end of the resistive memory cell, a bit line connected to another end of the resistive memory cell, and a sensing circuit connected to the source line and the bit line. The sensing circuit is configured to generate a pull-up signal that is pulled up from a first voltage level to a second voltage level, based on a read current flowing through the resistive memory cell, generate a pull-down signal that is pulled down from a third voltage level to a fourth voltage level, based on the read current, and determine data that is stored in the resistive memory cell, based on a difference between the generated pull-up signal and the generated pull-down signal.Type: ApplicationFiled: March 26, 2021Publication date: March 10, 2022Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventor: Chan Kyung KIM
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Patent number: 11194579Abstract: A memory device includes a memory cell array formed in a semiconductor die, the memory cell array including a plurality of memory cells to store data and a calculation circuit formed in the semiconductor die. The calculation circuit performs calculations based on broadcast data and internal data and omits the calculations with respect to invalid data and performs the calculations with respect to valid data based on index data in a skip calculation mode, where the broadcast data are provided from outside the semiconductor die, the internal data are read from the memory cell array, and the index data indicates whether the internal data are the valid data or the invalid data. Power consumption is reduced by omitting the calculations and the read operation with respect to the invalid data through the skip calculation mode based on the index data.Type: GrantFiled: November 26, 2018Date of Patent: December 7, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Hyun-Sung Shin, Sung-Ho Park, Chan-Kyung Kim, Yong-Sik Park, Sang-Hoon Shin
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Patent number: 11169711Abstract: A memory module includes a memory device, a command/address buffering device, and a processing data buffer. The memory device includes a memory cell array, a first set of input/output terminals, each terminal configured to receive first command/address bits, and a second set of input/output terminals, each terminal configured to receive both data bits and second command/address bits. The command/address buffering device is configured to output the first command/address bits to the first set of input/output terminals. The processing data buffer is configured to output the data bits and second command/address bits to the second set of input/output terminals. The memory device is configured such that the first command/address bits, second command/address bits, and data bits are all used to access the memory cell array.Type: GrantFiled: July 29, 2019Date of Patent: November 9, 2021Assignees: SAMSUNG ELECTRONICS CO., LTD., SNU R&D FOUNDATION, WISCONSIN ALUMNI RESEARCH FOUNDATIONInventors: Seong-Il O, Nam Sung Kim, Young-Hoon Son, Chan-Kyung Kim, Ho-Young Song, Jung Ho Ahn, Sang-Joon Hwang
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Publication number: 20210027823Abstract: Magnetic junction memory devices and methods for writing data to memory devices are provided. The magnetic junction memory device includes a first memory bank including first magnetic junction memory cells, a first local write driver adjacent to the first memory bank, connected to global data lines, the first local write driver configured to write data to the first magnetic junction memory cells via local data lines, a second memory bank adjacent to the first memory bank and including second magnetic junction memory cells, a second local write driver adjacent to the second memory bank, connected to the global data lines, the second local write driver configured to write data to the second magnetic junction memory cells via local data lines, and a global write driver configured to provide first and second write data to the first and second local write driver, respectively, via the global data lines.Type: ApplicationFiled: April 14, 2020Publication date: January 28, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Chan Kyung KIM, Ji Yean KIM, Hyun Taek JUNG, Ji Eun KIM, Tae Seong KIM, Sang-Hoon JUNG, Jae Wook JOO
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Publication number: 20210020692Abstract: A magnetic junction memory device is provided. The magnetic junction memory device including a sensing circuit including a sensing node, the sensing node being connected to a first end of a transistor and configured to change a voltage of the sensing node in accordance with a resistance of a magnetic junction memory cell, a gating voltage generator circuit configured to generate a gating voltage of the transistor using a reference resistor and a reference voltage, and a read circuit configured to read data from the magnetic junction memory cell using the reference voltage and the voltage of the sensing node.Type: ApplicationFiled: February 24, 2020Publication date: January 21, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Chan Kyung KIM, Eun Ji LEE, Ji Yean KIM, Tae Seong KIM, Jae Wook JOO
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Patent number: 10665575Abstract: A semiconductor package includes: a memory sub-package including a first connecting layer and a plurality of memory chips disposed on the first connecting layer; a logic sub-package including a second connecting layer, a controller chip disposed on the second connecting layer, and a buffer chip connected to the controller chip and the plurality of memory chips; and a plurality of inter-package connecting members each of which connects the memory sub-package and the logic sub-package, wherein the buffer chip is connected to the plurality of memory chips via a plurality of first data transfer lines each having a first data transfer rate, the buffer chip is connected to the controller chip via a plurality of second data transfer lines each having a second data transfer rate, and the first data transfer rate is less than the second data transfer rate.Type: GrantFiled: September 27, 2019Date of Patent: May 26, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Eun-seok Song, Chan-kyung Kim, Tae-joo Hwang
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Publication number: 20200160157Abstract: Provided is a memory device that includes a memory bank including a plurality of memory cells arranged in a region where a plurality of word lines and a plurality of bit lines of the memory device intersect each other, a sense amplifier configured to amplify a signal transmitted through selected bit lines among the plurality of bit lines, and an arithmetic circuit configured to receive a first operand from the sense amplifier, receive a second operand from outside the memory device, and perform an arithmetic operation by using the first operand and the second operand, based on an internal arithmetic control signal generated in the memory device.Type: ApplicationFiled: July 26, 2019Publication date: May 21, 2020Inventors: CHAN-KYUNG KIM, Soon-Young Kim, Jin-Min Kim, Jae-Hong Min, Sang-Kil Lee, Young-Nam Hwang
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Publication number: 20200027862Abstract: A semiconductor package includes: a memory sub-package including a first connecting layer and a plurality of memory chips disposed on the first connecting layer; a logic sub-package including a second connecting layer, a controller chip disposed on the second connecting layer, and a buffer chip connected to the controller chip and the plurality of memory chips; and a plurality of inter-package connecting members each of which connects the memory sub-package and the logic sub-package, wherein the buffer chip is connected to the plurality of memory chips via a plurality of first data transfer lines each having a first data transfer rate, the buffer chip is connected to the controller chip via a plurality of second data transfer lines each having a second data transfer rate, and the first data transfer rate is less than the second data transfer rate.Type: ApplicationFiled: September 27, 2019Publication date: January 23, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Eun-seok SONG, Chan-kyung KIM, Tae-joo HWANG
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Publication number: 20190354292Abstract: A memory module includes a memory device, a command/address buffering device, and a processing data buffer. The memory device includes a memory cell array, a first set of input/output terminals, each terminal configured to receive first command/address bits, and a second set of input/output terminals, each terminal configured to receive both data bits and second command/address bits. The command/address buffering device is configured to output the first command/address bits to the first set of input/output terminals. The processing data buffer is configured to output the data bits and second command/address bits to the second set of input/output terminals. The memory device is configured such that the first command/address bits, second command/address bits, and data bits are all used to access the memory cell array.Type: ApplicationFiled: July 29, 2019Publication date: November 21, 2019Applicants: SNU R&DB FOUNDATION, WISCONSIN ALUMNI RESEARCH FOUNDATIONInventors: Seong-Il O, Nam Sung KIM, Young-Hoon SON, Chan-Kyung KIM, Ho-Young SONG, Jung Ho AHN, Sang-Joon HWANG
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Patent number: 10475774Abstract: A semiconductor package includes: a memory sub-package including a first connecting layer and a plurality of memory chips disposed on the first connecting layer; a logic sub-package including a second connecting layer, a controller chip disposed on the second connecting layer, and a buffer chip connected to the controller chip and the plurality of memory chips; and a plurality of inter-package connecting members each of which connects the memory sub-package and the logic sub-package, wherein the buffer chip is connected to the plurality of memory chips via a plurality of first data transfer lines each having a first data transfer rate, the buffer chip is connected to the controller chip via a plurality of second data transfer lines each having a second data transfer rate, and the first data transfer rate is less than the second data transfer rate.Type: GrantFiled: September 18, 2018Date of Patent: November 12, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Eun-seok Song, Chan-kyung Kim, Tae-joo Hwang
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Patent number: 10446207Abstract: A magnetic random access memory (MRAM), and a memory module, memory system including the same, and method for controlling the same are disclosed. The MRAM includes magnetic memory cells configured to change between at least two states according to a magnetization direction, and a mode register supporting a plurality of operational modes.Type: GrantFiled: January 22, 2019Date of Patent: October 15, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chan-kyung Kim, Dong-seok Kang, Hye-jin Kim, Chul-woo Park, Dong-hyun Sohn, Yun-sang Lee, Sang-beom Kang, Hyung-rock Oh, Soo-ho Cha
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Patent number: 10416896Abstract: A memory module includes a memory device, a command/address buffering device, and a processing data buffer. The memory device includes a memory cell array, a first set of input/output terminals, each terminal configured to receive first command/address bits, and a second set of input/output terminals, each terminal configured to receive both data bits and second command/address bits. The command/address buffering device is configured to output the first command/address bits to the first set of input/output terminals. The processing data buffer is configured to output the data bits and second command/address bits to the second set of input/output terminals. The memory device is configured such that the first command/address bits, second command/address bits, and data bits are all used to access the memory cell array.Type: GrantFiled: May 23, 2017Date of Patent: September 17, 2019Assignees: Samsung Electronics Co., Ltd., SNU R&DB Foundation, Wisconsin Alumni Research FoundationInventors: Seong-Il O, Nam Sung Kim, Young-Hoon Son, Chan-Kyung Kim, Ho-Young Song, Jung Ho Ahn, Sang-Joon Hwang