Patents by Inventor Chan-kyung Kim

Chan-kyung Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11169711
    Abstract: A memory module includes a memory device, a command/address buffering device, and a processing data buffer. The memory device includes a memory cell array, a first set of input/output terminals, each terminal configured to receive first command/address bits, and a second set of input/output terminals, each terminal configured to receive both data bits and second command/address bits. The command/address buffering device is configured to output the first command/address bits to the first set of input/output terminals. The processing data buffer is configured to output the data bits and second command/address bits to the second set of input/output terminals. The memory device is configured such that the first command/address bits, second command/address bits, and data bits are all used to access the memory cell array.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: November 9, 2021
    Assignees: SAMSUNG ELECTRONICS CO., LTD., SNU R&D FOUNDATION, WISCONSIN ALUMNI RESEARCH FOUNDATION
    Inventors: Seong-Il O, Nam Sung Kim, Young-Hoon Son, Chan-Kyung Kim, Ho-Young Song, Jung Ho Ahn, Sang-Joon Hwang
  • Patent number: 11148122
    Abstract: A SCR catalyst for removing nitrogen oxides comprises: a carrier prepared from a support in which Ti-PILC is mixed with titania; and a catalyst material on the carrier, wherein the catalyst material contains an active material of a vanadium component and a co-catalyst of a tungsten component. On the basis of the total weight of the catalyst, the support Ti-PILC is contained at 0.01-40 wt %, and the support titania is contained at 50 to 90 wt %. In addition, a method for producing a SCR catalyst for removing nitrogen oxides comprises the steps of: preparing a carrier by using a support in which Ti-PILC is mixed with titania; and supporting a catalyst material on the carrier. The present disclosure provides: a SCR catalyst for removing nitrogen oxides, which has an excellent nitrogen oxide removing performance and a high producing convenience; and a method for producing the same.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: October 19, 2021
    Assignees: Korea Shipbuilding & Offshore Engineering Co., Ltd., Hyundai Heavy Industries Co., Ltd.
    Inventors: Sam Kyung Sung, Sang Ek Lee, Do Yun Kim, Hyun Soo Kim, Mong Kyu Chung, Chan Do Park
  • Publication number: 20210300933
    Abstract: The present disclosure provides a compound of Chemical Formula (1) or a pharmaceutically acceptable salt thereof, and a pharmaceutical composition comprising the same: wherein X, Z, R1 and R2 are as defined in the specification. The compound of Chemical Formula (1) or pharmaceutically acceptable salt thereof acts as a positive allosteric modulator of metabotropic glutamate receptor subtype 5 (mGluR5), thereby being useful in the prevention or treatment of disorder mediated by glutamate dysfunction and mGluR5.
    Type: Application
    Filed: June 1, 2021
    Publication date: September 30, 2021
    Inventors: Chun Eung PARK, Young Koo JANG, Yong Je SHIN, Ji Yeon KIM, Seung Mo HAM, Yong Gil KIM, Hye Kyung MIN, Soo Bong CHA, Hyo Jun JUNG, Ju Young LEE, Seung Nam HAN, Jin Yong CHUNG, Eun Ju CHOI, Chan Mi JOUNG, Jong Sil PARK, Ji Won LEE, Nahm Ryune CHO, Eun Ju RYU, Cheol Young MAENG
  • Patent number: 11096921
    Abstract: The present invention relates to a compound of Formula 1, and an SIRT 1 activator including, as an active ingredient, derivatives thereof or pharmaceutically acceptable salts thereof. The present invention also relates to a composition including the SIRT 1 activator for detoxification, for the improvement of metabolic disorders, for the prevention or improvement of eye diseases, or the prevention or improvement of immune diseases.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: August 24, 2021
    Assignee: AMOREPACIFIC CORPORATION
    Inventors: Byung Gyu Kim, Hyun Woo Jeong, Su Kyung Kim, Si Young Cho, Chan Woong Park, Dae Bang Seo, Wan Gi Kim, Sang Jun Lee
  • Publication number: 20210027823
    Abstract: Magnetic junction memory devices and methods for writing data to memory devices are provided. The magnetic junction memory device includes a first memory bank including first magnetic junction memory cells, a first local write driver adjacent to the first memory bank, connected to global data lines, the first local write driver configured to write data to the first magnetic junction memory cells via local data lines, a second memory bank adjacent to the first memory bank and including second magnetic junction memory cells, a second local write driver adjacent to the second memory bank, connected to the global data lines, the second local write driver configured to write data to the second magnetic junction memory cells via local data lines, and a global write driver configured to provide first and second write data to the first and second local write driver, respectively, via the global data lines.
    Type: Application
    Filed: April 14, 2020
    Publication date: January 28, 2021
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Chan Kyung KIM, Ji Yean KIM, Hyun Taek JUNG, Ji Eun KIM, Tae Seong KIM, Sang-Hoon JUNG, Jae Wook JOO
  • Publication number: 20210020692
    Abstract: A magnetic junction memory device is provided. The magnetic junction memory device including a sensing circuit including a sensing node, the sensing node being connected to a first end of a transistor and configured to change a voltage of the sensing node in accordance with a resistance of a magnetic junction memory cell, a gating voltage generator circuit configured to generate a gating voltage of the transistor using a reference resistor and a reference voltage, and a read circuit configured to read data from the magnetic junction memory cell using the reference voltage and the voltage of the sensing node.
    Type: Application
    Filed: February 24, 2020
    Publication date: January 21, 2021
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Chan Kyung KIM, Eun Ji LEE, Ji Yean KIM, Tae Seong KIM, Jae Wook JOO
  • Patent number: 10665575
    Abstract: A semiconductor package includes: a memory sub-package including a first connecting layer and a plurality of memory chips disposed on the first connecting layer; a logic sub-package including a second connecting layer, a controller chip disposed on the second connecting layer, and a buffer chip connected to the controller chip and the plurality of memory chips; and a plurality of inter-package connecting members each of which connects the memory sub-package and the logic sub-package, wherein the buffer chip is connected to the plurality of memory chips via a plurality of first data transfer lines each having a first data transfer rate, the buffer chip is connected to the controller chip via a plurality of second data transfer lines each having a second data transfer rate, and the first data transfer rate is less than the second data transfer rate.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: May 26, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eun-seok Song, Chan-kyung Kim, Tae-joo Hwang
  • Publication number: 20200160157
    Abstract: Provided is a memory device that includes a memory bank including a plurality of memory cells arranged in a region where a plurality of word lines and a plurality of bit lines of the memory device intersect each other, a sense amplifier configured to amplify a signal transmitted through selected bit lines among the plurality of bit lines, and an arithmetic circuit configured to receive a first operand from the sense amplifier, receive a second operand from outside the memory device, and perform an arithmetic operation by using the first operand and the second operand, based on an internal arithmetic control signal generated in the memory device.
    Type: Application
    Filed: July 26, 2019
    Publication date: May 21, 2020
    Inventors: CHAN-KYUNG KIM, Soon-Young Kim, Jin-Min Kim, Jae-Hong Min, Sang-Kil Lee, Young-Nam Hwang
  • Publication number: 20200027862
    Abstract: A semiconductor package includes: a memory sub-package including a first connecting layer and a plurality of memory chips disposed on the first connecting layer; a logic sub-package including a second connecting layer, a controller chip disposed on the second connecting layer, and a buffer chip connected to the controller chip and the plurality of memory chips; and a plurality of inter-package connecting members each of which connects the memory sub-package and the logic sub-package, wherein the buffer chip is connected to the plurality of memory chips via a plurality of first data transfer lines each having a first data transfer rate, the buffer chip is connected to the controller chip via a plurality of second data transfer lines each having a second data transfer rate, and the first data transfer rate is less than the second data transfer rate.
    Type: Application
    Filed: September 27, 2019
    Publication date: January 23, 2020
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eun-seok SONG, Chan-kyung KIM, Tae-joo HWANG
  • Publication number: 20190354292
    Abstract: A memory module includes a memory device, a command/address buffering device, and a processing data buffer. The memory device includes a memory cell array, a first set of input/output terminals, each terminal configured to receive first command/address bits, and a second set of input/output terminals, each terminal configured to receive both data bits and second command/address bits. The command/address buffering device is configured to output the first command/address bits to the first set of input/output terminals. The processing data buffer is configured to output the data bits and second command/address bits to the second set of input/output terminals. The memory device is configured such that the first command/address bits, second command/address bits, and data bits are all used to access the memory cell array.
    Type: Application
    Filed: July 29, 2019
    Publication date: November 21, 2019
    Applicants: SNU R&DB FOUNDATION, WISCONSIN ALUMNI RESEARCH FOUNDATION
    Inventors: Seong-Il O, Nam Sung KIM, Young-Hoon SON, Chan-Kyung KIM, Ho-Young SONG, Jung Ho AHN, Sang-Joon HWANG
  • Patent number: 10475774
    Abstract: A semiconductor package includes: a memory sub-package including a first connecting layer and a plurality of memory chips disposed on the first connecting layer; a logic sub-package including a second connecting layer, a controller chip disposed on the second connecting layer, and a buffer chip connected to the controller chip and the plurality of memory chips; and a plurality of inter-package connecting members each of which connects the memory sub-package and the logic sub-package, wherein the buffer chip is connected to the plurality of memory chips via a plurality of first data transfer lines each having a first data transfer rate, the buffer chip is connected to the controller chip via a plurality of second data transfer lines each having a second data transfer rate, and the first data transfer rate is less than the second data transfer rate.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: November 12, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eun-seok Song, Chan-kyung Kim, Tae-joo Hwang
  • Patent number: 10446207
    Abstract: A magnetic random access memory (MRAM), and a memory module, memory system including the same, and method for controlling the same are disclosed. The MRAM includes magnetic memory cells configured to change between at least two states according to a magnetization direction, and a mode register supporting a plurality of operational modes.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: October 15, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chan-kyung Kim, Dong-seok Kang, Hye-jin Kim, Chul-woo Park, Dong-hyun Sohn, Yun-sang Lee, Sang-beom Kang, Hyung-rock Oh, Soo-ho Cha
  • Patent number: 10416896
    Abstract: A memory module includes a memory device, a command/address buffering device, and a processing data buffer. The memory device includes a memory cell array, a first set of input/output terminals, each terminal configured to receive first command/address bits, and a second set of input/output terminals, each terminal configured to receive both data bits and second command/address bits. The command/address buffering device is configured to output the first command/address bits to the first set of input/output terminals. The processing data buffer is configured to output the data bits and second command/address bits to the second set of input/output terminals. The memory device is configured such that the first command/address bits, second command/address bits, and data bits are all used to access the memory cell array.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: September 17, 2019
    Assignees: Samsung Electronics Co., Ltd., SNU R&DB Foundation, Wisconsin Alumni Research Foundation
    Inventors: Seong-Il O, Nam Sung Kim, Young-Hoon Son, Chan-Kyung Kim, Ho-Young Song, Jung Ho Ahn, Sang-Joon Hwang
  • Publication number: 20190259737
    Abstract: A semiconductor package includes: a memory sub-package including a first connecting layer and a plurality of memory chips disposed on the first connecting layer; a logic sub-package including a second connecting layer, a controller chip disposed on the second connecting layer, and a buffer chip connected to the controller chip and the plurality of memory chips; and a plurality of inter-package connecting members each of which connects the memory sub-package and the logic sub-package, wherein the buffer chip is connected to the plurality of memory chips via a plurality of first data transfer lines each having a first data transfer rate, the buffer chip is connected to the controller chip via a plurality of second data transfer lines each having a second data transfer rate, and the first data transfer rate is less than the second data transfer rate.
    Type: Application
    Filed: September 18, 2018
    Publication date: August 22, 2019
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eun-seok Song, Chan-kyung Kim, Tae-joo Hwang
  • Publication number: 20190258487
    Abstract: A memory device includes a memory cell array formed in a semiconductor die, the memory cell array including a plurality of memory cells to store data and a calculation circuit formed in the semiconductor die. The calculation circuit performs calculations based on broadcast data and internal data and omits the calculations with respect to invalid data and performs the calculations with respect to valid data based on index data in a skip calculation mode, where the broadcast data are provided from outside the semiconductor die, the internal data are read from the memory cell array, and the index data indicates whether the internal data are the valid data or the invalid data. Power consumption is reduced by omitting the calculations and the read operation with respect to the invalid data through the skip calculation mode based on the index data.
    Type: Application
    Filed: November 26, 2018
    Publication date: August 22, 2019
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Sung SHIN, Sung-Ho PARK, Chan-Kyung KIM, Yong-Sik PARK, Sang-Hoon SHIN
  • Patent number: 10372658
    Abstract: A method and a memory device therefor for reconfiguring a DQ pad organization of the memory device on-the-fly. A DQ organization reconfiguration control unit generates a control signal for reconfiguring the DQ pad organization into a desired mode based on a user command. A DQ organization reconfiguration unit is provided between P DQ pads and memory cell arrays and reconfigures organization P DQ pads on-the-fly in any one among Xi DQ pad modes, where i=1, 2, 4, 8, 16, 32, 64, and 128, based on the control signal. For the reconfiguration of the organization of the DQ pads, a plurality of bus lines for data transfer, being switchable by a control signal, are provided. The bus lines are implemented utilizing at least one of the M3 and M4 metal layers of the memory device.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: August 6, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Chan-Kyung Kim
  • Patent number: 10204670
    Abstract: A magnetic random access memory (MRAM), and a memory module, memory system including the same, and method for controlling the same are disclosed. The MRAM includes magnetic memory cells configured to change between at least two states according to a magnetization direction, and a mode register supporting a plurality of operational modes.
    Type: Grant
    Filed: February 15, 2013
    Date of Patent: February 12, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chan-kyung Kim, Dong-seok Kang, Hye-jin Kim, Chul-woo Park, Dong-hyun Sohn, Yun-sang Lee, Sang-beom Kang, Hyung-rock Oh, Soo-ho Cha
  • Patent number: 10090035
    Abstract: A semiconductor device includes a bit-line sense amplifier (S/A) circuit configured to sense and amplify data stored in a resistive memory cell according to a reference current. The bit-line S/A circuit includes a cross-coupled latch circuit and a write latch circuit. The cross-coupled latch circuit is coupled to an input/output circuit via a first line and a complementary first line. The cross-coupled latch circuit is configured to receive write data via the first line, and to latch the write data during a data write operation. The write latch circuit is coupled to the cross-coupled latch circuit, and configured to store the write data in the resistive memory cell via a second line during the data write operation.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: October 2, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Chan Kyung Kim
  • Publication number: 20180189219
    Abstract: A method and a memory device therefor for reconfiguring a DQ pad organization of the memory device on-the-fly. A DQ organization reconfiguration control unit generates a control signal for reconfiguring the DQ pad organization into a desired mode based on a user command. A DQ organization reconfiguration unit is provided between P DQ pads and memory cell arrays and reconfigures organization P DQ pads on-the-fly in any one among Xi DQ pad modes, where i=1, 2, 4, 8, 16, 32, 64, and 128, based on the control signal. For the reconfiguration of the organization of the DQ pads, a plurality of bus lines for data transfer, being switchable by a control signal, are provided. The bus lines are implemented utilizing at least one of the M3 and M4 metal layers of the memory device.
    Type: Application
    Filed: August 15, 2017
    Publication date: July 5, 2018
    Inventor: Chan-Kyung Kim
  • Publication number: 20180107406
    Abstract: A memory module includes a memory device, a command/address buffering device, and a processing data buffer. The memory device includes a memory cell array, a first set of input/output terminals, each terminal configured to receive first command/address bits, and a second set of input/output terminals, each terminal configured to receive both data bits and second command/address bits. The command/address buffering device is configured to output the first command/address bits to the first set of input/output terminals. The processing data buffer is configured to output the data bits and second command/address bits to the second set of input/output terminals. The memory device is configured such that the first command/address bits, second command/address bits, and data bits are all used to access the memory cell array.
    Type: Application
    Filed: May 23, 2017
    Publication date: April 19, 2018
    Applicants: SNU R&DB FOUNDATION, WISCONSIN ALUMIN RESEARCH FOUNDATION
    Inventors: SEONG-IL O, Nam Sung KIM, Young-Hoon SON, Chan-Kyung KIM, Ho-Young SONG, Jung Ho AHN, Sang-Joon HWANG