Abstract: A method of dispersing semiconductor chips from a wafer of semiconductor chips onto a substrate while preserving the neighboring relationship of each chip to each adjacent chip is disclosed. The method includes dispersing the wafer into sequential columns of semiconductor chips with a first pitch between columns while preserving the neighboring relationship and sequentially dispersing the columns of semiconductor chips into rows of individual chips with a second pitch between rows onto a substrate while preserving the neighboring relationship.

Abstract: A method of fabricating a high mobility semiconductor metal oxide thin film transistor including the steps of depositing a layer of semiconductor metal oxide material, depositing a blanket layer of etch-stop material on the layer of MO material, and patterning a layer of source/drain metal on the blanket layer of etch-stop material including etching the layer of source/drain metal into source/drain terminals positioned to define a channel area in the semiconductor metal oxide layer. The etch-stop material being electrically conductive in a direction perpendicular to the plane of the blanket layer at least under the source/drain terminals to provide electrical contact between each of the source/drain terminals and the layer of semiconductor metal oxide material. The etch-stop material is also chemical robust to protect the layer of semiconductor metal oxide channel material during the etching process.

Abstract: A method of fabricating a structure including a high mobility backplane and a-Si photodiode imager includes forming a matrix of metal oxide thin film transistors on the surface of a rigid support member, depositing a planarizing layer on the matrix of transistors that is either porous or permissive/diffusive to oxygen at temperatures below approximately 200° C., and fabricating a matrix of passivated a-Si photodiodes over the matrix of transistors and electrically connected one each photodiode to each of the transistors. A continuous path is provided through the planarizing layer from the exterior of the structure to each of the transistors and the structure is annealed at a temperature below 200° C. in an oxygen ambient to move oxygen from the oxygen ambient to an active layer of each of the transistors and repair loss of oxygen damage to the transistors caused by the fabrication of the passivated a-Si photodiodes.

Abstract: A method of fabricating a structure including a high mobility backplane and a-Si photodiode imager includes forming a matrix of metal oxide thin film transistors on the surface of a rigid support member, depositing a planarizing layer on the matrix of transistors that is either porous or permissive/diffusive to oxygen at temperatures below approximately 200° C., and fabricating a matrix of passivated a-Si photodiodes over the matrix of transistors and electrically connected one each photodiode to each of the transistors. A continuous path is provided through the planarizing layer from the exterior of the structure to each of the transistors and the structure is annealed at a temperature below 200° C. in an oxygen ambient to move oxygen from the oxygen ambient to an active layer of each of the transistors and repair loss of oxygen damage to the transistors caused by the fabrication of the passivated a-Si photodiodes.

Abstract: A metal oxide semiconductor device including an active layer of metal oxide, a layer of gate dielectric, and a layer of low trap density material. The layer of low trap density material is sandwiched between the active layer of metal oxide and the layer of gate dielectric. The layer of low trap density material has a major surface parallel and in contact with a major surface of the active layer of metal oxide to form a low trap density interface with the active layer of metal oxide. A second layer of low trap density material can optionally be placed in contact with the opposed major surface of the active layer of metal oxide so that a low trap density interface is formed with both surfaces of the active layer of metal oxide.

Abstract: Apparatus for fluorescent and ion sensing of DNA nucleotide incorporation events including DNA nucleotide incorporation structure designed to have sequencing primers bonded to a surface for the incorporation of DNA nucleotides thereon. At least some of the DNA nucleotides having a fluorescent label. A photodiode positioned adjacent the incorporation structure and an illumination device positioned adjacent the DNA nucleotide incorporation structure to illuminate DNA nucleotides incorporated onto the sequencing primers. The illumination device exciting the fluorescent labels when incorporation occurs and the photodiode positioned to sense the excited fluorescent labels. Ion sensing apparatus positioned adjacent the DNA nucleotide incorporation structure including a metal oxide thin film transistor with a gate electrically coupled to receive an electrical signal indicative of ion emissions produced by the DNA nucleotide incorporated onto DNA target fragments or sequencing primers.

Abstract: A metal oxide TFT-based sensor with multiple sensing modalities including an ion sensitive detector having an extended gate, a reservoir constructed to receive a sample carrying solution, and an ion sensitive electrode. The sensor further including a photodiode, a plurality of metal-oxide thin film transistors and a signal output. A pair of the metal-oxide thin film transistors are coupled to the photodiode, the ion sensitive detector and the output so as to provide output signals at the output alternately representative of ion emissions sensed by the ion sensitive detector and fluorescence events sensed by the photodiode.

Abstract: A method of passivating a MOTFT including providing a metal oxide thin film transistor having a surface defined by spaced apart source/drain terminals positioned on a layer of semiconductor metal oxide and material in a space between the source/drain terminals, the space between the source/drain terminals defining a conduction channel in the layer of semiconductor metal oxide. Forming a layer of passivation material on the surface defined by the spaced apart source/drain terminals and the material in the space between the source/drain terminals. Establishing oxygen vacancy equilibrium in the conduction channel of the layer of semiconductor metal oxide by annealing in an oxygen containing ambient the MOTFT and layer of passivation material and depositing a layer including a noble metal, a refractory metal, and/or a transparent conducting metal oxide on the layer of passivation material overlying the space between the source/drain terminals.

Abstract: A method of fabricating a pixelated imager and structure including a substrate with a bottom contact layer and active element blanket layers deposited on the bottom contact layer. The blanket layers are separated into an array of active elements with trenches isolating adjacent active elements in the array. A dielectric passivation/planarization layer is positioned over the array of active elements. An array of active element readout circuits overlies the passivation/planarization layer above the trenches with one active element readout circuit coupled to each active element of the array of active elements. Each active element and coupled active element readout circuit defines a pixel and the array of active elements and the coupled array of active element readout circuits defines a pixelated imager, and the readout circuit coupled to each active element includes at least one TFT with an active channel comprising a metal-oxide semiconductor material.

Abstract: A thin film circuit includes a thin film transistor with a metal oxide semiconductor channel having a conduction band minimum (CBM) with a first energy level. The transistor further includes a layer of passivation material covering at least a portion of the metal oxide semiconductor channel. The passivation material has a conduction band minimum (CBM) with a second energy level. The second energy level being lower than, equal to, or no more than 0.5 eV above the first energy level. The circuit is used for an electronic device including any one of an AMLCD, AMOLED, AMLED, AMEPD.

Abstract: A method including providing a substrate with a gate, a layer of gate insulator material adjacent the gate, and a layer of metal oxide semiconductor material positioned on the gate insulator opposite the gate, forming a selectively patterned etch stop passivation layer and heating at elevated temperature in an oxygen-containing or nitrogen-containing or inert ambience to selectively increase the carrier concentration in regions of the metal oxide semiconductor not covered by the etch stop layer, on which overlying and spaced apart source/drain metals are formed. Subsequently heating the transistor in an oxygen-containing or nitrogen-containing or inert ambience to further improve the source/drain contacts and adjust the threshold voltage to a desired level. Providing additional passivation layer(s) on top of the transistor with electric insulation and barrier property to moisture and chemicals in the surrounding environment.

Abstract: A full-color AM OLED includes a transparent substrate, a color filter positioned on an upper surface of the substrate, and a metal oxide thin film transistor backpanel positioned in overlying relationship on the color filter and defining an array of pixels. An array of OLEDs is formed on the backpanel and positioned to emit light downwardly through the backpanel, the color filter, and the substrate in a full-color display. Light emitted by each OLED includes a first emission band with wavelengths extending across the range of two of the primary colors and a second emission band with wavelengths extending across the range of the remaining primary color. The color filter includes for each pixel, two zones separating the first emission band into two separate primary colors and a third zone passing the second emission band.

Abstract: Two-terminal electronic devices, such as photodetectors, photovoltaic devices and electroluminescent devices, are provided. The devices include a first electrode residing on a substrate, wherein the first electrode comprises a layer of metal; an I-layer comprising an inorganic insulating or broad band semiconducting material residing on top of the first electrode, and aligned with the first electrode, wherein the inorganic insulating or broad band semiconducting material is a compound of the metal of the first electrode; a semiconductor layer, preferably comprising a p-type semiconductor, residing over the I-layer; and a second electrode residing over the semiconductor layer, the electrode comprising a layer of a conductive material. The band gap of the material of the semiconductor layer, is preferably smaller than the band gap of the I-layer material. The band gap of the material of the I-layer is preferably greater than 2.5 eV.

Abstract: A method of fabricating MO TFTs includes positioning opaque gate metal on a transparent substrate to define a gate area. Depositing gate dielectric material overlying the gate metal and a surrounding area, and depositing metal oxide semiconductor material thereon. Depositing etch stop material on the semiconductor material. Positioning photoresist defining an isolation area in the semiconductor material, the etch stop material and the photoresist being selectively removable. Exposing the photoresist from the rear surface of the substrate and removing exposed portions to leave the etch stop material uncovered except for a portion overlying and aligned with the gate metal. Etching uncovered portions of the semiconductor material to isolate the TFT. Using the photoresist, selectively etching the etch stop layer to leave a portion overlying and aligned with the gate metal and defining a channel area in the semiconductor material. Depositing and patterning conductive material to form source and drain areas.

Abstract: The process of fabricating a flexible TFT back-panel includes depositing etch stop material on a glass support. A matrix of contact pads, gate electrodes and gate dielectric are deposited overlying the etch stop material. Vias are formed through the dielectric in communication with each pad. A matrix of TFTs is formed by depositing and patterning metal oxide semiconductor material to form an active layer of each TFT overlying the gate electrode. Source/drain metal is deposited on the active layer and in the vias in contact with the pads, the source/drain metal defining source/drain terminals of each TFT. Passivation material is deposited in overlying relationship to the TFTs. A color filter layer is formed on the passivation material and a flexible plastic carrier is affixed to the color filter. The glass support member and the etch stop material are then etched away to expose a surface of each of the pads.

Abstract: A method of fabricating a high mobility semiconductor metal oxide thin film transistor including the steps of depositing a layer of semiconductor metal oxide material, depositing a blanket layer of etch-stop material on the layer of MO material, and patterning a layer of source/drain metal on the blanket layer of etch-stop material including etching the layer of source/drain metal into source/drain terminals positioned to define a channel area in the semiconductor metal oxide layer. The etch-stop material being electrically conductive in a direction perpendicular to the plane of the blanket layer at least under the source/drain terminals to provide electrical contact between each of the source/drain terminals and the layer of semiconductor metal oxide material. The etch-stop material is also chemical robust to protect the layer of semiconductor metal oxide channel material during the etching process.

Abstract: A method of fabricating a stable high mobility amorphous MOTFT includes a step of providing a substrate with a gate formed thereon and a gate dielectric layer positioned over the gate. A carrier transport structure is deposited by sputtering on the gate dielectric layer. The carrier transport structure includes a layer of amorphous high mobility metal oxide adjacent the gate dielectric and a relatively inert protective layer of material deposited on the layer of amorphous high mobility metal oxide both deposited without oxygen and in situ. The layer of amorphous metal oxide has a mobility above 40 cm2/Vs and a carrier concentration in a range of approximately 1018 cm?3 to approximately 5×1019 cm?3. Source/drain contacts are positioned on the protective layer and in electrical contact therewith.

Abstract: A method including providing a substrate with a gate, a layer of gate insulator material adjacent the gate, and a layer of metal oxide semiconductor material positioned on the gate insulator opposite the gate, forming a selectively patterned etch stop passivation layer and heating at elevated temperature in an oxygen-containing or nitrogen-containing or inert ambience to selectively increase the carrier concentration in regions of the metal oxide semiconductor not covered by the etch stop layer, on which overlying and spaced apart source/drain metals are formed. Subsequently heating the transistor in an oxygen-containing or nitrogen-containing or inert ambience to further improve the source/drain contacts and adjust the threshold voltage to a desired level. Providing additional passivation layer(s) on top of the transistor with electric insulation and barrier property to moisture and chemicals in the surrounding environment.

Abstract: A method of fabricating an X-ray imager including the steps of forming an etch stop layer on a glass substrate and depositing a stack of semiconductor layers on the etch stop layer to form a sensor plane. Separating the stack into an array of PIN photodiodes. Depositing a layer of insulating material on the array to form a planarized surface and forming vias through the insulating layer into communication with an upper surface of each photodiode and forming metal contacts on the planarized surface through the vias in contact with each photodiode. Fabricating an array of MOTFTs in an active pixel sensor configuration backplane on the planarized surface and in electrical communication with the contacts, to provide a sensor plane/MOTFT backplane interconnected combination. Attaching a flexible support carrier to the MOTFT backplane and removing the glass substrate. A scintillator is then laminated on the array of photodiodes.

Abstract: Electro-chemical manipulation and charge sensing apparatus includes a chemical/biochemical testing pad positioned on a dielectric substrate, a sensing circuit coupled to the testing pad, the sensing circuit including at least one MOTFT device, and a manipulation and control circuit coupled to the testing pad, the manipulation and control circuit including at least one MOTFT device. The electro-chemical manipulation and charge sensing apparatus can include a plurality of chemical/biochemical testing pads distributed in a matrix formation of rows and columns and positioned on a dielectric substrate.