Abstract: A semiconductor device, and a method of operating the same, includes a memory cell array, a peripheral circuit, and control logic. The memory cell array includes a plurality of memory cells. The peripheral circuit is configured to perform a program operation on memory cells selected from among the plurality of memory cells. The control logic is configured to control the program operation of the peripheral circuit. The control logic is configured to control the peripheral circuit to precharge bit lines respectively coupled to the selected memory cells to different voltage levels during a verify operation included in the program operation.

Abstract: A memory device includes: a memory cell array including a plurality of memory cells; a peripheral circuit including a plurality of page buffers respectively connected to the plurality of memory cells through a plurality of bit lines and a voltage generating circuit for selectively outputting a program voltage and a verify voltage; and a control circuit configured to control the peripheral circuit to perform a plurality of program loops each including a program voltage apply operation and a verify operation. Each of the plurality of page buffers may include: a first latch for storing a verify result according to the verify operation of an nth program loop among the plurality of program loops; and a second latch for storing a verify result according to the verify operation of an (n?1)th program loop among the plurality of program loops.

Abstract: Provided herein may be a memory device for performing a program operation including program loops and a method of operating the same. The method of operating a memory device may include performing a first program loop of increasing threshold voltages of first memory cells selected by a first drain select line among a plurality of memory cells coupled to a word line, performing a second program loop of increasing threshold voltages of second memory cells selected by a second drain select line among the plurality of memory cells, and alternately repeating the first program loop and the second program loop such that respective threshold voltages of the first memory cells and the second memory cells are increased to respective threshold voltages corresponding to respective target program states.

Abstract: A memory device includes: a memory cell array including a plurality of memory cells; a peripheral circuit including a plurality of page buffers respectively connected to the plurality of memory cells; a sensing circuit connected to the plurality of page buffers respectively, the sensing circuit: performing a sensing operation on the page buffers in units of a plurality of chunks, each chunk including two or more page buffers, among the plurality of page buffers, and outputting a sensing result of each of the plurality of chunks; a verification result output circuit for outputting a final verification result of a target program state, among a plurality of program states to which the memory cells are to be programmed, based on the sensing results of the plurality of chunks; and a control logic for controlling the sensing circuit and the peripheral circuit, based on the final verification result.

Abstract: Provided herein is a memory device for performing a program operation, a method of operating the memory device, and a storage device having the memory device. The method of operating a memory device includes receiving a first data bit among a plurality of data bits to be stored in each of a plurality of memory cells from a memory controller, performing a program voltage apply operation on the plurality of memory cells based on the first data bit, and receiving a second data bit among the plurality of data bits from the memory controller while performing the program voltage apply operation.

Abstract: Provided herein is a memory device and a method of operating the memory device. The memory device includes memory cells coupled to a word line, a peripheral circuit configured to perform a program operation of increasing threshold voltages of the memory cells to threshold voltages corresponding to a target program state among a plurality of program states, and a program operation controller configured to determine whether to perform an erase state verify operation of identifying threshold voltages of erase cells having an erase state as the target program state among the memory cells.

Abstract: A semiconductor device, and a method of operating the same, includes a memory cell array, a peripheral circuit, and control logic. The memory cell array includes a plurality of memory cells. The peripheral circuit is configured to perform a program operation on memory cells selected from among the plurality of memory cells. The control logic is configured to control the program operation of the peripheral circuit. The control logic is configured to control the peripheral circuit to precharge bit lines respectively coupled to the selected memory cells to different voltage levels during a verify operation included in the program operation.

Abstract: Methods, systems, and devices are disclosed for implementing semiconductor memory using variable resistance elements for storing data. In one aspect, an electronic device is provided to comprise a semiconductor memory unit including: a substrate; an interlayer dielectric layer disposed over the substrate; and a variable resistance element including a seed layer formed over the interlayer dielectric layer, a first magnetic layer formed over the seed layer, a tunnel barrier layer formed over the first magnetic layer, and a second magnetic layer formed over the tunnel barrier layer, wherein the seed layer includes a conductive material having a metallic property and an oxygen content of 1% to approximately 10%.

Abstract: Methods, systems, and devices are disclosed for implementing semiconductor memory using variable resistance elements for storing data. In one aspect, an electronic device is provided to comprise a semiconductor memory unit including: a substrate; an interlayer dielectric layer disposed over the substrate; and a variable resistance element including a seed layer formed over the interlayer dielectric layer, a first magnetic layer formed over the seed layer, a tunnel barrier layer formed over the first magnetic layer, and a second magnetic layer formed over the tunnel barrier layer, wherein the seed layer includes a conductive material having a metallic property and an oxygen content of 1% to approximately 10%.

Abstract: A method of performing embedded compression (EC) on image data includes receiving decoded image data; determining a block size of image data waiting for embedded compression from among the received image data; and comparing the determined block size of the image data waiting for embedded compression with an EC block size that is an embedded compression unit, the method further including: if the determined block size of the image data waiting for embedded compression is equal to or greater than the EC block size, embedding and compressing the received image data; and if the determined block size of the image data waiting for embedded compression is smaller than the EC block size, storing tag information of the received image data.

Abstract: Methods, systems, and devices are disclosed for implementing semiconductor memory using variable resistance elements for storing data. In one aspect, an electronic device is provided to comprise a semiconductor memory unit including: a substrate; an interlayer dielectric layer disposed over the substrate; and a variable resistance element including a seed layer formed over the interlayer dielectric layer, a first magnetic layer formed over the seed layer, a tunnel barrier layer formed over the first magnetic layer, and a second magnetic layer formed over the tunnel barrier layer, wherein the seed layer includes a conductive material having a metallic property and an oxygen content of 1% to approximately 10%.

Abstract: According to an embodiment of the present disclosure, an electronic device may comprise a memory and a processor configured to produce compressed data by compressing data including a first block and a second block stored in the memory, wherein the processor may be configured to include a first replacement data table corresponding to first sub-data in the compressed data, the first sub-data included in the first block, and the first replacement data table produced based on, at least, rankings of first frequencies for the first sub-data, and include information for reference to the first replacement data table, corresponding to the second block, when second sub-data included in the second block and rankings of second frequencies for the second sub-data meet a designated condition with respect to the first sub-data included in the first block and the rankings of the first frequencies. Other embodiments are also possible.

Abstract: A video decoding method includes obtaining a motion vector of a current block belonging to a first picture from a bitstream, performed by a first decoding unit; determining whether a reference block indicated by the motion vector is decoded, performed by the first decoding unit; and decoding the current block, based on whether the reference block is decoded. The reference block is included in a second picture decoded by a second decoding unit. The first picture and the second picture are decoded in parallel.

Abstract: Electronic devices and systems having semiconductor memory are provided. In one implementation, for example, an electronic device may include a substrate; an under layer disposed over the substrate and including conductive hafnium silicate; a free layer disposed over the under layer and having a variable magnetization direction; a tunnel barrier layer disposed over the free layer; and a pinned layer disposed over the tunnel barrier layer and having a pinned magnetization direction, and wherein the free layer includes: a first ferromagnetic material; a second ferromagnetic material having a coercive force smaller than that of the first ferromagnetic material; and an amorphous spacer interposed between the first ferromagnetic material and the second ferromagnetic material.

Abstract: Provided are a method and an apparatus for decoding an image by accessing a memory by a block group. The method comprises checking information regarding a size of one or more blocks included in a bitstream of an encoded image, determining whether to group one or more blocks for performing decoding, based on the information regarding the size of the one or more blocks, setting a block group including one or more blocks based on the information regarding the size of the one or more blocks, and accessing a memory by the block group to perform a parallel-pipeline decoding process by the block group.

Abstract: According to an embodiment of the present disclosure, an electronic device may comprise a memory and a processor configured to produce compressed data by compressing data including a first block and a second block stored in the memory, wherein the processor may be configured to include a first replacement data table corresponding to first sub-data in the compressed data, the first sub-data included in the first block, and the first replacement data table produced based on, at least, rankings of first frequencies for the first sub-data, and include information for reference to the first replacement data table, corresponding to the second block, when second sub-data included in the second block and rankings of second frequencies for the second sub-data meet a designated condition with respect to the first sub-data included in the first block and the rankings of the first frequencies. Other embodiments are also possible.

Abstract: A method of performing embedded compression (EC) on image data includes receiving decoded image data; determining a block size of image data waiting for embedded compression from among the received image data; and comparing the determined block size of the image data waiting for embedded compression with an EC block size that is an embedded compression unit, the method further including: if the determined block size of the image data waiting for embedded compression is equal to or greater than the EC block size, embedding and compressing the received image data; and if the determined block size of the image data waiting for embedded compression is smaller than the EC block size, storing tag information of the received image data.

Abstract: Electronic devices and systems having semiconductor memory are provided. In one implementation, for example, an electronic device may include a substrate; an under layer disposed over the substrate and including conductive hafnium silicate; a free layer disposed over the under layer and having a variable magnetization direction; a tunnel barrier layer disposed over the free layer; and a pinned layer disposed over the tunnel barrier layer and having a pinned magnetization direction, and wherein the free layer includes: a first ferromagnetic material; a second ferromagnetic material having a coercive force smaller than that of the first ferromagnetic material; and an amorphous spacer interposed between the first ferromagnetic material and the second ferromagnetic material.

Abstract: Electronic devices and systems having semiconductor memory are provided. In one implementation, for example, an electronic device may include a substrate; an under layer disposed over the substrate and including conductive hafnium silicate; a free layer disposed over the under layer and having a variable magnetization direction; a tunnel barrier layer disposed over the free layer; and a pinned layer disposed over the tunnel barrier layer and having a pinned magnetization direction, and wherein the free layer includes: a first ferromagnetic material; a second ferromagnetic material having a coercive force smaller than that of the first ferromagnetic material; and an amorphous spacer interposed between the first ferromagnetic material and the second ferromagnetic material.

Abstract: Disclosed is a fuel processor. The fuel processor includes: a steam reformer unit configured to be disposed at an upper portion in a casing; a heat exchanger unit configured to be disposed at a lower portion of the steam reformer unit; a high temperature shift reforming unit configured to be disposed at a lower portion of the heat exchanger unit; a low temperature shift reforming unit configured to be disposed while enclosing an outer portion of the high temperature shift reforming unit; and a heat exchange chamber configured to be disposed at a lower portion of the high temperature shift reforming unit and exchange heat between reformed gas and a heat exchange fluid supplied through a channel part formed to drain the reformed gas and combustion gas and supply the heat exchange fluid.