Abstract: A light-emitting device includes a substrate; a light-emitting unit formed on the substrate, comprising a first conductivity type semiconductor; a second conductivity type semiconductor; an active layer formed between the first and the second conductivity type semiconductors; and an exposed region formed in the light-emitting unit, exposing the first conductivity type semiconductor; a first electrode extending layer formed on the first conductivity type semiconductor in the exposed region; a second electrode extending layer formed on the second conductivity type semiconductor; a transparent insulator, formed on the light-emitting unit and filled in the exposed region; a first electrode formed on the transparent insulator; and a plurality of conductive channel layers formed in the transparent insulator; wherein one of the plurality of conductive channel layers connects the first electrode and one of the first and the second electrode extending layers.

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated circuit. The method is performed by forming a gate structure over a substrate, and selectively implanting the substrate according to the gate structure to form first and second source/drain regions on opposing sides of the gate structure. A first MEOL structure is formed on the first source/drain region and a second MEOL structure is formed on the second source/drain region. The first MEOL structure has a bottommost surface that extends in a first direction from directly over the first source/drain region to laterally past an outermost edge of the first source/drain region. A conductive structure is formed to contact the first MEOL structure and the second MEOL structure. The conductive structure laterally extends from directly over the first MEOL structure to directly over the second MEOL structure along a second direction perpendicular to the first direction.

Abstract: A semiconductor device includes first and second transistors, a pair of first source/drain regions, a pair of second source/drain regions, and a cell. Each of the first source/drain regions corresponds to a first source/drain terminal of a respective one of the first and second transistors. Each of the second source/drain regions corresponds to a second source/drain terminal of a respective one of the first and second transistors. The cell includes a first voltage rail, a pair of second voltage rails, and a cell circuit. The first voltage rail is coupled to the first source/drain regions. Each of the second voltage rails is coupled to a respective one of the second source/drain regions and is configured to be coupled to the first voltage rail. The cell circuit is coupled to one of the second voltage rails.

Abstract: The present invention relates to a dye-sensitized solar cell electrode, and more particularly, to a dye-sensitized solar cell electrode capable of enhancing a bond between a dye and an oxide semiconductor to secure reliability and efficiency of a dye-sensitized solar cell.

Abstract: A gas turbine includes a bearing housing surrounding an outside of a tie rod provided on the turbine. One end of a power strut is connected to an outside of the bearing housing, and the other end is radially arranged outwards. A cooling-air supply unit supplies cooling air to the power strut. A heat exchange unit is disposed in the power strut to perform a heat exchange process with cooling air supplied through the cooling-air supply unit. A ring-shaped support frame is connected to the other end of the power strut.

Abstract: A device is disclosed that includes a memory bit cell, a first word line, a pair of metal islands and a pair of connection metal lines. The first word line is disposed in a first metal layer and is electrically coupled to the memory bit cell. The pair of metal islands are disposed in the first metal layer at opposite sides of the word line and are electrically coupled to a power supply. The pair of connection metal lines are disposed in a second metal layer and are configured to electrically couple the metal islands to the memory bit cell respectively.

Abstract: An integrated circuit structure includes a set of rails, a first and second set of conductive structures and a first set of vias. The set of rails extends in a first direction and is located at a first level. Each rail of the set of rails is separated from one another in a second direction. The first set of conductive structures extends in the second direction, overlaps the set of rails and is located at a second level. The first set of vias is between the set of rails and the first set of conductive structures. Each of the first set of vias is located where each of the first set of conductive structures overlaps each of the set of rails. The first set of vias couple the first set of conductive structures to the set of rails. The second set of conductive structures is between the set of rails.

Abstract: An integrated circuit structure includes a set of gate structures, a first conductive structure, a first and second set of vias, and a first set of conductive structures. The set of gate structures is located at a first level. The first conductive structure extends in a first direction, overlaps the set of gate structures and is located at a second level. The first set of vias is between the set of gate structures and the first conductive structure. The first set of vias couple the set of gate structures to the first conductive structure. The first set of conductive structures extend in a second direction, overlap the first conductive structure, and is located at a third level. The second set of vias couple the first set of conductive structures to the first conductive structure, and is between the first set of conductive structures and the first conductive structure.

Abstract: A semiconductor device includes first and second transistors, a pair of first source/drain regions, a pair of second source/drain regions, and a cell. Each of the first source/drain regions corresponds to a first source/drain terminal of a respective one of the first and second transistors. Each of the second source/drain regions corresponds to a second source/drain terminal of a respective one of the first and second transistors. The cell includes a first voltage rail, a pair of second voltage rails, and a cell circuit. The first voltage rail is coupled to the first source/drain regions. Each of the second voltage rails is coupled to a respective one of the second source/drain regions and is configured to be coupled to the first voltage rail. The cell circuit is coupled to one of the second voltage rails.

Abstract: Semiconductor structures and methods for forming a semiconductor structure are provided. A first active semiconductor region is disposed in a first vertical level of the semiconductor structure. A second active semiconductor region is disposed in the first vertical level, where the second active semiconductor region is separated from the first active semiconductor region by a distance in a first direction. A first conductive structure is disposed in a second vertical level that is adjacent to the first vertical level. The first conductive structure extends along the first direction and electrically couples the first active semiconductor region to the second active semiconductor region.

Abstract: A layout method includes: selecting, by a processor or manual, a first layout device in a layout of an integrated circuit; selecting a second device abutting the first layout device at a boundary between the first layout device and the second layout device, wherein a conductive path is disposed across the boundary of the first layout device and the second layout device; and disposing a cut layer on the conductive path and nearby the boundary. The first layout device is a first layout pattern and the second layout device is a second layout pattern different from the first layout pattern.

Abstract: A semiconductor device includes a substrate and fins. The fins are formed on a first area and a second area of the substrate. The first area includes a first recess. The second area is located with respect to the first area. The first recess is disposed at a side of the first area, and faces the second area. A projection area of the first recess on a side of the second area is substantially flat.

Abstract: In some embodiments, the present disclosure relates to an integrated circuit (IC) having parallel conductive paths between a BEOL interconnect layer and a middle-end-of-the-line (MEOL) structure, which are configured to reduce a parasitic resistance and/or capacitance of the IC. The IC comprises source/drain regions arranged within a substrate and separated by a channel region. A gate structure is arranged over the channel region and a MEOL structure is arranged over one of the source/drain regions. A conductive structure is arranged over and in electrical contact with the MEOL structure. A first conductive contact is arranged between the MEOL structure and an overlying BEOL interconnect wire (e.g., a power rail). A second conductive contact is configured to electrically couple the BEOL interconnect wire and the MEOL structure along a conductive path extending through the conductive structure, thereby forming parallel conductive paths between the BEOL interconnect layer and the MEOL structure.

Abstract: An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.

Abstract: A method and an apparatus for performing hybrid automatic repeat request (HARQ) in a wireless communication system is provided. UEs that use the same application for D2D communications form a sharing group so that reliability of transmission of a physical uplink shared channel (PUSCH) and a physical uplink control channel (PUCCH) among terminals that perform the D2D communications is guaranteed. In addition, among the terminals that perform the D2D communications, uplink transmission points in time determined in accordance with TDD configuration are checked and determined (calculated) so that the PUSCH and the PUCCH are correctly transmitted and received.

Abstract: A light-emitting device includes a substrate; a light-emitting unit formed on the substrate, comprising a first conductivity type semiconductor; a second conductivity type semiconductor; an active layer formed between the first and the second conductivity type semiconductors; and an exposed region formed in the light-emitting unit, exposing the first conductivity type semiconductor; a first electrode extending layer formed on the first conductivity type semiconductor in the exposed region; a second electrode extending layer formed on the second conductivity type semiconductor; a transparent insulator, formed on the light-emitting unit and filled in the exposed region; a first electrode formed on the transparent insulator; and a plurality of conductive channel layers formed in the transparent insulator; wherein one of the plurality of conductive channel layers connects the first electrode and one of the first and the second electrode extending layers.

Abstract: An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.

Abstract: Disclosed herein is a refined product obtained from a rice hull, which consists essentially of a type II arabinogalactan having a number average molecular weight in the range of 56 to 103 kDa. Also disclosed are a process for producing the refined product and use of the refined product for enhancing the biological activity of innate immune cells, as well as for treating allergy and cancer.

Abstract: Provided are an apparatus and method for supplying a light-emitting diode (LED) wafer that may quickly and accurately transfer LED wafers by acquiring position information of pockets in a carrier in which the LED wafers are to be seated. The apparatus may include a cassette in which a plurality of LED wafers are loaded, a carrier including a plurality of pockets in which the LED wafers are seated, an aligning unit to align the LED wafers that are to be seated in the carrier, a transfer robot to transfer the LED wafers from the cassette to the aligning unit, a picker to hold, in an adsorbed state, the LED wafers transferred to the aligning unit, or to release the adsorbed state, a capturing unit to fix the picker, and to acquire position information of the pockets, and an LED wafer loading robot to transfer the picker and the capturing unit from the aligning unit to the carrier.

Abstract: A light-emitting diode (LED) wafer picker that may increase a suction force and may perform stable adsorption without a concern for contact with a top surface of an LED wafer is provided. An LED wafer picker may include a main body to hold, in an adsorbed state, an LED wafer disposed below the main body, when air drawn in from a top of the LED wafer picker is discharged along a streamlined discharge surface to both sides of the LED wafer picker, a guide member to enable the air to flow along the discharge surface, the guide member being disposed below the discharge surface, a single central hole formed in a central portion of the guide member, excluding a portion facing the discharge surface, and a support portion to support the LED wafer, the support portion extending downward from the guide member. Accordingly, it is possible to easily perform adsorption of an LED wafer that is relatively far from the LED wafer picker.