Abstract: The disclosure relates to decentralized management of edge nodes operating outside an enterprise network using blockchain technology. A management node may operate within a firewall of the enterprise to manage the edge nodes operating outside the firewall using blockchain technology. The management node may coordinate management by writing change requests to a decentralized ledger. The edge nodes may read the change requests from its local copy of the distributed ledger and implement the change requests. Upon implementation, an edge node may broadcast its status to the blockchain network. The management node may mine the transactions from the edge nodes into the distributed ledger, thereby creating a secure and scalable way to coordinate management and record the current and historical system state. The system also provides the edge nodes with a cryptographically secured, machine-to-machine maintained, single version of truth, enabling them to take globally valid decision based on local data.

Abstract: A power semiconductor device and a method of manufacturing a power semiconductor device is provided, including a shield gate trench (SGT) metal-oxide semiconductor field-effect transistor (MOSFET). The present disclosure provides for a MOSFET with a reduced charge between the gate conductive region and the drain or collector region, in order to improve the switching efficiency of the MOSFET.

Abstract: A method of manufacturing a semiconductor power device is provided. The method includes forming at least two trench regions within a semiconductor region, etching each trench region so that the mesa region extends above an upper surface of each trench region, and forming a plurality of spacers, where the spacers are located over each trench region and are adjacent to the mesa region.

Abstract: Some embodiments include an integrated assembly having a carrier-sink-structure, and having digit lines over the carrier-sink-structure. Transistor body regions are over the digit lines. Extensions extend from the carrier-sink-structure to the transistor body regions. The extensions are configured to drain excess carriers from the transistor body regions. Lower source/drain regions are between the transistor body regions and the digit lines, and are coupled with the digit lines. Upper source/drain regions are over the transistor body regions, and are coupled with storage elements. Gates are adjacent the transistor body regions. The transistor body regions, lower source/drain regions and upper source/drain regions are together comprised a plurality of transistors. The transistors and the storage elements are together comprised by a plurality of memory cells of a memory array. Some embodiments include methods of forming integrated assemblies.

Abstract: There is provided a method of manufacturing a manufacturing intermediate for a semiconductor package, the method including: providing a die; at least partially encapsulating the die within a moulding compound; and thinning the die. There is further provided a manufacturing intermediate for a semiconductor package, including: a die having a first surface and a second surface; and a moulding encapsulating the die; in which the first surface of the die is exposed.

Abstract: An example apparatus includes a first source/drain region and a second source/drain region formed in a substrate to form an active area of the apparatus. The first source/drain region and the second source/drain region are separated by a channel. The apparatus includes a gate opposing the channel. A sense line is coupled to the first source/drain region and a storage node is coupled to the second source/drain region. An isolation trench is adjacent to the active area. The trench includes a dielectric material with a conductive bias opposing the conductive bias of the channel in the active area.

Abstract: An array of vertical transistors comprises spaced pillars individually comprising a channel region of individual vertical transistors. A horizontally-elongated conductor line directly electrically couples together individual of the channel regions of the pillars of a plurality of the vertical transistors. An upper source/drain region is above the individual channel regions of the pillars, a lower source/drain region is below the individual channel regions of the pillars, and a conductive gate line is operatively aside the individual channel regions of the pillars and that interconnects multiple of the vertical transistors. Methods are disclosed.

Abstract: A semiconductor power device is provided, including a drift region of a first conductivity, a body region of a second conductivity type disposed over the drift region, the second type is opposite to the first type, at least two gate trench regions in contact with the body and the drift region, and two laterally adjacent gate trench regions are separated by a mesa region, a contact region of a first conductivity type located in the mesa region and disposed over the body region, the contact region has a higher doping concentration compared to the concentration of the drift region, and the contact region is in contact with the two adjacent gate trench regions so that, in use, a channel is formed along each gate trench region and within the body region; and a source contact disposed over the contact region, and an auxiliary gate region formed within the mesa region.

Abstract: A trench transistor with nonlinear gate-oxide-semiconductor boundary layout, and method of manufacture is provided. The trench transistor includes a gate region, an oxide region adjacent to the gate region, and a semiconductor region adjacent to the oxide region. The semiconductor region includes a channel region along a gate-oxide-semiconductor boundary. The channel region is configured to conduct current along the gate-oxide-semiconductor boundary when the transistor is turned on. The gate-oxide-semiconductor boundary has a nonlinear shape.

Abstract: A trench transistor with nonlinear gate-oxide-semiconductor boundary layout, and method of manufacture is provided. The trench transistor includes a gate region, an oxide region adjacent to the gate region, and a semiconductor region adjacent to the oxide region. The semiconductor region includes a channel region along a gate-oxide-semiconductor boundary. The channel region is configured to conduct current along the gate-oxide-semiconductor boundary when the transistor is turned on. The gate-oxide-semiconductor boundary has a nonlinear shape.

Abstract: Some embodiments include an integrated assembly having a carrier-sink-structure, and having digit lines over the carrier-sink-structure. Transistor body regions are over the digit lines. Extensions extend from the carrier-sink-structure to the transistor body regions. The extensions are configured to drain excess carriers from the transistor body regions. Lower source/drain regions are between the transistor body regions and the digit lines, and are coupled with the digit lines. Upper source/drain regions are over the transistor body regions, and are coupled with storage elements. Gates are adjacent the transistor body regions. The transistor body regions, lower source/drain regions and upper source/drain regions are together comprised a plurality of transistors. The transistors and the storage elements are together comprised by a plurality of memory cells of a memory array. Some embodiments include methods of forming integrated assemblies.

Abstract: Some embodiments include an integrated assembly having a carrier-sink-structure, and having digit lines over the carrier-sink-structure. Transistor body regions are over the digit lines. Extensions extend from the carrier-sink-structure to the transistor body regions. The extensions are configured to drain excess carriers from the transistor body regions. Lower source/drain regions are between the transistor body regions and the digit lines, and are coupled with the digit lines. Upper source/drain regions are over the transistor body regions, and are coupled with storage elements. Gates are adjacent the transistor body regions. The transistor body regions, lower source/drain regions and upper source/drain regions are together comprised a plurality of transistors. The transistors and the storage elements are together comprised by a plurality of memory cells of a memory array. Some embodiments include methods of forming integrated assemblies.

Abstract: An example apparatus includes a first source/drain region and a second source/drain region formed in a substrate to form an active area of the apparatus. The first source/drain region and the second source/drain region are separated by a channel. The apparatus includes a gate opposing the channel. A sense line is coupled to the first source/drain region and a storage node is coupled to the second source/drain region. An isolation trench is adjacent to the active area. The trench includes a dielectric material with a conductive bias opposing the conductive bias of the channel in the active area.

Abstract: An example apparatus includes a first source/drain region and a second source/drain region formed in a substrate to form an active area of the apparatus. The first source/drain region and the second source/drain region are separated by a channel. The apparatus includes a gate opposing the channel. A sense line is coupled to the first source/drain region and a storage node is coupled to the second source/drain region. An isolation trench is adjacent to the active area. The trench includes a dielectric material with a conductive bias opposing the conductive bias of the channel in the active area.

Abstract: The disclosure relates to decentralized management of nodes in a blockchain network. Participants may agree to a consensus rules and implement them as smart contracts. For example, one rule may specify that a node will accept a change proposal only when its local policies and/or data allow it to implement the change. A smart contract may implement this rule and deploy it across the blockchain network for each node to follow. Other participants, through their nodes, may propose changes to the blockchain network, and each node may consult its copy of the smart contract to determine whether to vote to approve the change request and apply the change request locally.

Abstract: A variety of applications can include apparatus having a transistor comprising a modified channel region to address sub-surface leakage issues of the transistor. A dielectric region can be structured to extend from a channel structure of the transistor downward into the substrate for the transistor, with the dielectric region disposed between the source of the transistor and the drain of the transistor to reduce leakage current paths between the source and the drain. The dielectric region can be structured with only dielectric material or with crystalline semiconductor material surrounded by dielectric material.

Abstract: An apparatus comprises active word lines extending within a semiconductive material, passing word lines extending adjacent to the active word lines within the semiconductive material, isolation regions adjacent to the passing word lines, and a band offset material adjacent to the passing word lines and the isolation regions. The semiconductive material exhibits a first bandgap and the band offset material exhibits a second, different bandgap. Related methods and systems are also described.

Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices having a first source/drain region and a second source drain region separated by a channel region, and gates opposing the channel region, vertically oriented access lines coupled to the gates and separated from a channel region by a gate dielectric. The memory cells have horizontally oriented storage nodes coupled to the second source/drain region and horizontally oriented digit lines coupled to the first source/drain regions. In one example, an insulator material is formed on a surface of the first source/drain region and a conductor material formed on the insulator material to form a metal insulator semiconductor (MIS) interface between the horizontally oriented digit lines and the first source/drain regions of the horizontally oriented access devices.

Abstract: Some embodiments include an integrated assembly having a polycrystalline first semiconductor material, and having a second semiconductor material directly adjacent to the polycrystalline first semiconductor material. The second semiconductor material is of a different composition than the polycrystalline first semiconductor material. A conductivity-enhancing dopant is within the second semiconductor material. The conductivity-enhancing dopant is a neutral-type dopant relative to the polycrystalline first semiconductor material. An electrical gate is adjacent to a region of the polycrystalline first semiconductor material and is configured to induce an electric field within said region of the polycrystalline first semiconductor material. The gate is not adjacent to the second semiconductor material.

Abstract: Systems, apparatuses, and methods related to semiconductor structure formation are described. An example apparatus includes a first trench and a second trench formed in a semiconductor substrate material, where the first and second trenches are adjacent and separated by the semiconductor substrate material. The apparatus includes a metallic material formed to a first height in the first trench that is less than, relative to the semiconductor substrate material, a second height of the metallic material formed in the second trench and a polysilicon material formed over the metallic material in the first trench to a first depth greater than, relative to the semiconductor substrate material, a second depth of the polysilicon material formed over the metallic material in the second trench. The greater first depth of the polysilicon material formed in the first trench reduces transfer of charge by way of the metallic material in the first trench.