Patents by Inventor Chandra Pandey

Chandra Pandey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180130807
    Abstract: Some embodiments include a transistor having a semiconductor material with a trench extending downwardly therein. The semiconductor material has a first post region on one side of the trench and a second post region on an opposing side of the trench. The semiconductor material has a narrow fin region along the bottom of the trench and extending between the first and second post regions. Each of the first and second post regions has a first thickness and the narrow fin region has a second thickness, with the second thickness being less than the first thickness. Gate dielectric material is along sidewalls of the first and second post regions, along a top of the narrow fin region, and along side surfaces of the narrow fin region. Gate material is over the gate dielectric material. First and second source/drain regions are within the first and second post regions.
    Type: Application
    Filed: November 9, 2017
    Publication date: May 10, 2018
    Inventor: Deepak Chandra Pandey
  • Publication number: 20170358532
    Abstract: An electronic component of integrated circuitry comprises a substrate comprising at least two terminals. Material of one of the terminals has an upper surface. A conductive via extends elevationally into the material of the one terminal. The conductive via extends laterally into the material of the one terminal under the upper surface of the one terminal. Material of the one terminal is above at least some of the laterally extending conductive via. Other embodiments, including method embodiments, are disclosed.
    Type: Application
    Filed: August 3, 2017
    Publication date: December 14, 2017
    Inventors: Deepak Chandra Pandey, Haitao Liu
  • Patent number: 9842840
    Abstract: Some embodiments include a transistor having a semiconductor material with a trench extending downwardly therein. The semiconductor material has a first post region on one side of the trench and a second post region on an opposing side of the trench. The semiconductor material has a narrow fin region along the bottom of the trench and extending between the first and second post regions. Each of the first and second post regions has a first thickness and the narrow fin region has a second thickness, with the second thickness being less than the first thickness. Gate dielectric material is along sidewalls of the first and second post regions, along a top of the narrow fin region, and along side surfaces of the narrow fin region. Gate material is over the gate dielectric material. First and second source/drain regions are within the first and second post regions.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: December 12, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Deepak Chandra Pandey
  • Patent number: 9787488
    Abstract: In general, techniques are described for simplifying admission control signaling between subscriber devices, access nodes, and service edge routers to facilitate subscriber-specific admission control for multicast streams. In one example, a service edge router receives a service request and accesses a subscriber profile to determine whether the requesting subscriber is authorized to receive the service. Upon authorization, the service edge router returns the service request to the access node in a substantially similar form in which the service request was received. The access node receives the service request on a service edge router-facing interface, indicating the service edge router has granted authorization for the subscriber device to receive multicast traffic associated with the multicast group identified within the service request.
    Type: Grant
    Filed: August 11, 2014
    Date of Patent: October 10, 2017
    Assignee: Juniper Networks, Inc.
    Inventors: George Rainovic, Chandra Pandey
  • Patent number: 9754889
    Abstract: An electronic component of integrated circuitry comprises a substrate comprising at least two terminals. Material of one of the terminals has an upper surface. A conductive via extends elevationally into the material of the one terminal. The conductive via extends laterally into the material of the one terminal under the upper surface of the one terminal. Material of the one terminal is above at least some of the laterally extending conductive via. Other embodiments, including method embodiments, are disclosed.
    Type: Grant
    Filed: December 19, 2015
    Date of Patent: September 5, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Deepak Chandra Pandey, Haitao Liu
  • Publication number: 20170179031
    Abstract: An electronic component of integrated circuitry comprises a substrate comprising at least two terminals. Material of one of the terminals has an upper surface. A conductive via extends elevationally into the material of the one terminal. The conductive via extends laterally into the material of the one terminal under the upper surface of the one terminal. Material of the one terminal is above at least some of the laterally extending conductive via. Other embodiments, including method embodiments, are disclosed.
    Type: Application
    Filed: December 19, 2015
    Publication date: June 22, 2017
    Inventors: Deepak Chandra Pandey, Haitao Liu
  • Patent number: 9449978
    Abstract: A semiconductor device comprises a recessed access device that includes a first pillar, a second pillar, a channel region connecting the first and second pillars, and a gate disposed over the channel region. The channel region has a width that is narrower than widths of the first pillar and the second pillar. An array of recessed access devices comprises a plurality of pillars protruding from a substrate, and a plurality of channel regions. Each channel region has a width that is less than about 10 nm and couples neighboring pillars to form a plurality of junctionless recessed access devices. A method of forming at least one recessed access device also comprises forming pillars over a substrate, forming at least a channel region coupled with the pillars, the channel region having a relatively narrow width, and forming a gate at least partially surrounding the channel region on at least three sides.
    Type: Grant
    Filed: January 6, 2014
    Date of Patent: September 20, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Mingtao Li, Haitao Liu, Deepak Chandra Pandey, Mark Fischer
  • Patent number: 9414355
    Abstract: Disclosed herein are methods and systems for paging a wireless communication device in a radio access network based on a communication type. An example method may include a radio access network receiving a request to initiate a communication with a wireless communication device. The example method may also include the radio access network determining a type of the requested communication. The example method may additionally include the radio access network determining a maximum number of page attempts for a paging process of the wireless communication device based on at least the determined type. The example method may further include the radio access network initiating the paging process of the wireless communication.
    Type: Grant
    Filed: October 22, 2013
    Date of Patent: August 9, 2016
    Assignee: Sprint Spectrum L.P.
    Inventor: Chandra Pandey
  • Patent number: 9391206
    Abstract: Some embodiments include methods of forming transistors. Recesses are formed to extend into semiconductor material. The recesses have upper regions lined with liner material and have segments of semiconductor material exposed along lower regions. Semiconductor material is isotropically etched through the exposed segments which transforms the recesses into openings having wide lower regions beneath narrow upper regions. Gate dielectric material is formed along sidewalls of the openings. Gate material is formed within the openings and over regions of the semiconductor material between the openings. Insulative material is formed down the center of each opening and entirely through the gate material. A segment of gate material extends from one of the openings to the other, and wraps around a pillar of the semiconductor material between the openings. The segment is a gate of a transistor. Source/drain regions are formed on opposing sides of the gate.
    Type: Grant
    Filed: January 11, 2016
    Date of Patent: July 12, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Deepak Chandra Pandey, Haitao Liu, Fawad Ahmed, Kamal M. Karda
  • Publication number: 20160126354
    Abstract: Some embodiments include methods of forming transistors. Recesses are formed to extend into semiconductor material. The recesses have upper regions lined with liner material and have segments of semiconductor material exposed along lower regions. Semiconductor material is isotropically etched through the exposed segments which transforms the recesses into openings having wide lower regions beneath narrow upper regions. Gate dielectric material is formed along sidewalls of the openings. Gate material is formed within the openings and over regions of the semiconductor material between the openings. Insulative material is formed down the center of each opening and entirely through the gate material. A segment of gate material extends from one of the openings to the other, and wraps around a pillar of the semiconductor material between the openings. The segment is a gate of a transistor. Source/drain regions are formed on opposing sides of the gate.
    Type: Application
    Filed: January 11, 2016
    Publication date: May 5, 2016
    Inventors: Deepak Chandra Pandey, Haitao Liu, Fawad Ahmed, Kamal M. Karda
  • Patent number: 9263341
    Abstract: Some embodiments include methods of forming transistors. Recesses are formed to extend into semiconductor material. The recesses have upper regions lined with liner material and have segments of semiconductor material exposed along lower regions. Semiconductor material is isotropically etched through the exposed segments which transforms the recesses into openings having wide lower regions beneath narrow upper regions. Gate dielectric material is formed along sidewalls of the openings. Gate material is formed within the openings and over regions of the semiconductor material between the openings. Insulative material is formed down the center of each opening and entirely through the gate material. A segment of gate material extends from one of the openings to the other, and wraps around a pillar of the semiconductor material between the openings. The segment is a gate of a transistor. Source/drain regions are formed on opposing sides of the gate.
    Type: Grant
    Filed: August 26, 2015
    Date of Patent: February 16, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Deepak Chandra Pandey, Haitao Liu, Fawad Ahmed, Kamal M. Karda
  • Patent number: 9258267
    Abstract: A network device establishes a logical channel with each server device of multiple server devices, where each logical channel is not shared with another server device of the multiple server devices. The network device also determines a network loopback Internet protocol (IP) address for each server device of the multiple server devices, and associates each network loopback IP address with a corresponding logical channel. The network device further receives a packet destined for a particular server device, and provides the packet to the particular server device via the logical channel associated with the particular server device.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: February 9, 2016
    Assignee: Juniper Networks, Inc.
    Inventors: George Rainovic, Chandra Pandey
  • Publication number: 20150364377
    Abstract: Some embodiments include methods of forming transistors. Recesses are formed to extend into semiconductor material. The recesses have upper regions lined with liner material and have segments of semiconductor material exposed along lower regions. Semiconductor material is isotropically etched through the exposed segments which transforms the recesses into openings having wide lower regions beneath narrow upper regions. Gate dielectric material is formed along sidewalls of the openings. Gate material is formed within the openings and over regions of the semiconductor material between the openings. Insulative material is formed down the center of each opening and entirely through the gate material. A segment of gate material extends from one of the openings to the other, and wraps around a pillar of the semiconductor material between the openings. The segment is a gate of a transistor. Source/drain regions are formed on opposing sides of the gate.
    Type: Application
    Filed: August 26, 2015
    Publication date: December 17, 2015
    Inventors: Deepak Chandra Pandey, Haitao Liu, Fawad Ahmed, Kamal M. Karda
  • Publication number: 20150194430
    Abstract: A semiconductor device comprises a recessed access device that includes a first pillar, a second pillar, a channel region connecting the first and second pillars, and a gate disposed over the channel region. The channel region has a width that is narrower than widths of the first pillar and the second pillar. An array of recessed access devices comprises a plurality of pillars protruding from a substrate, and a plurality of channel regions. Each channel region has a width that is less than about 10 nm and couples neighboring pillars to form a plurality of junctionless recessed access devices. A method of forming at least one recessed access device also comprises forming pillars over a substrate, forming at least a channel region coupled with the pillars, the channel region having a relatively narrow width, and forming a gate at least partially surrounding the channel region on at least three sides.
    Type: Application
    Filed: January 6, 2014
    Publication date: July 9, 2015
    Applicant: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Mingtao Li, Haitao Liu, Deepak Chandra Pandey, Mark Fischer
  • Patent number: 8983461
    Abstract: Range indicators for sectors in a wireless network may be determined by measuring, in a plurality of test locations, signal strengths of pilot signals transmitted by the sectors. Each sector's determined range indicator may be stored as a predefined range indicator for the sector in association with a list of predefined neighbors for the sector. When a candidate sector is added to a mobile station's active set, a neighbor list may be constructed for the mobile station, by taking into account the predefined range indicator for the candidate sector. If the predefined range indicator indicates that the candidate sector has a standard range, then the candidate sector's predefined neighbors may be added to the neighbor list. If the predefined range indicator indicates that the candidate sector has a non-standard range (e.g., indicating a “boomer”), then the candidate sector's predefined neighbors may be omitted from the neighbor list.
    Type: Grant
    Filed: February 11, 2013
    Date of Patent: March 17, 2015
    Assignee: Sprint Spectrum L.P.
    Inventors: Chandra Pandey, Sandeep Goyal
  • Patent number: 8904446
    Abstract: An approach provides indexing of media content capable of effectively controlling playback availability of the vast variety of media content. A recording of a video session associated with a media stream is initiated. A portion of the video session is selected. And an index for playback of the selected portion and for playback of the video session is configured, wherein the selected portion is played back when the video session is unavailable for playback.
    Type: Grant
    Filed: May 30, 2012
    Date of Patent: December 2, 2014
    Assignee: Verizon Patent and Licensing Inc.
    Inventor: Chandra Pandey
  • Patent number: 8804720
    Abstract: In general, techniques are described for simplifying admission control signaling between subscriber devices, access nodes, and service edge routers to facilitate subscriber-specific admission control for multicast streams. In one example, a service edge router receives a service request and accesses a subscriber profile to determine whether the requesting subscriber is authorized to receive the service. Upon authorization, the service edge router returns the service request to the access node in a substantially similar form in which the service request was received. The access node receives the service request on a service edge router-facing interface, indicating the service edge router has granted authorization for the subscriber device to receive multicast traffic associated with the multicast group identified within the service request.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: August 12, 2014
    Assignee: Juniper Networks, Inc.
    Inventors: George Rainovic, Chandra Pandey
  • Patent number: 8612612
    Abstract: In one example, a method includes receiving, with a network device, a portion of a subscriber session packet flow for a subscriber session, and reassembling application-layer data from data packets in the subscriber session packet flow into one or more application flows for the subscriber session. The method includes identifying, from the application flows, application identity information for the application flows, and applying a first session policy to the subscriber session. Applying the first session policy includes applying one or more application policies to the application flows in the subscriber session based on subscriber information and the application identity information for the application flows. The method includes processing the application flows in the subscriber session for accessing a packet data network in accordance with the application policies.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: December 17, 2013
    Assignee: Juniper Networks, Inc.
    Inventors: Mohini Dukes, Chandra Pandey, Vijay Kamisetty
  • Patent number: 8601133
    Abstract: A network device establishes a logical channel with each server device of multiple server devices, where each logical channel is not shared with another server device of the multiple server devices. The network device also determines a network loopback Internet protocol (IP) address for each server device of the multiple server devices, and associates each network loopback IP address with a corresponding logical channel. The network device further receives a packet destined for a particular server device, and provides the packet to the particular server device via the logical channel associated with the particular server device.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: December 3, 2013
    Assignee: Juniper Networks, Inc.
    Inventors: George Rainovic, Chandra Pandey
  • Publication number: 20120115045
    Abstract: Disclosed herein are methods and devices for generating electricity from an effluent source. In the presence of a biological catalyst, a high strength effluent allows for efficient production of electricity. Further, disclosed herein are methods for the treatment of wastewater while generating electricity.
    Type: Application
    Filed: January 27, 2011
    Publication date: May 10, 2012
    Inventors: Piyush Kumar R. KAPOPARA, Mrityunjay Kumar Singh, Vinayak Gupta, Hemant Giri, Ramesh Chandra Pandey