Patents by Inventor Chandrasekharan Kothandaraman

Chandrasekharan Kothandaraman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060197179
    Abstract: The present invention provides a dense semiconductor fuse array having common cathodes. The dense semiconductor fuse array of the present invention occupies less area than conventional semiconductor fuse arrays, can comprise integrated diodic components, and can require only one metal wiring layer for making electrical connections to the fuse array.
    Type: Application
    Filed: March 3, 2005
    Publication date: September 7, 2006
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Byeongju Park, Chandrasekharan Kothandaraman, Subramanian Iyer
  • Publication number: 20060158239
    Abstract: An integrated circuit device having at least one fuse capable of being blown in order to provide measurements of fuse current-voltage characteristics is provided. The integrated circuit device also provides at least one pulse generation circuit associated with the fuse and capable of generating a pulse to blow the fuse through one or more DC input signals.
    Type: Application
    Filed: January 18, 2005
    Publication date: July 20, 2006
    Applicant: International Business Machines Corporation
    Inventors: Manjul Bhushan, Mark Ketchen, Chandrasekharan Kothandaraman, Edward Maciejewski
  • Patent number: 7075127
    Abstract: An electrically programmable transistor fuse having a double-gate arrangement disposed in a single layer of polysilicon in which a first gate is disposed overlapping a portion of a source region and a second gate is insulated from the first gate and disposed overlapping a portion of a drain region. The first gate includes a terminal for receiving an externally applied control signal and the second gate is capacitively couple to the drain region in which a coupling device is included for increasing the capacitive coupling of the second gate and the drain region for enabling reduction in fuse programming voltage.
    Type: Grant
    Filed: January 29, 2004
    Date of Patent: July 11, 2006
    Assignee: Infineon Technologies AG
    Inventors: Chandrasekharan Kothandaraman, Danny Shum
  • Publication number: 20060136751
    Abstract: Techniques and systems whereby operation of and/or access to particular features of an electronic device may be controlled after the device has left the control of the manufacturer are provided. The operation and/or access may be provided based on values stored in non-volatile storage elements, such as electrically programmable fused (eFUSES).
    Type: Application
    Filed: December 17, 2004
    Publication date: June 22, 2006
    Applicant: International Business Machines Corporation
    Inventors: Anthony Bonaccio, Karl Erickson, John Fifield, Chandrasekharan Kothandaraman, Phil Paone, William Tonti
  • Publication number: 20060136858
    Abstract: Techniques and systems whereby operation of and/or access to particular features of an electronic device may be controlled after the device has left the control of the manufacturer are provided. The operation and/or access may be provided based on values stored in non-volatile storage elements, such as electrically programmable fused (eFUSES).
    Type: Application
    Filed: December 17, 2004
    Publication date: June 22, 2006
    Applicant: International Business Machines Corporation
    Inventors: Karl Erickson, John Fifield, Chandrasekharan Kothandaraman, Phil Paone, William Tonti
  • Publication number: 20060131743
    Abstract: Techniques and systems whereby operation of and/or access to particular features of an electronic device may be controlled after the device has left the control of the manufacturer are provided. The operation and/or access may be provided based on values stored in non-volatile storage elements, such as electrically programmable fused (eFUSES).
    Type: Application
    Filed: December 17, 2004
    Publication date: June 22, 2006
    Applicant: International Business Machines Corporation
    Inventors: Karl Erickson, John Fifield, Chandrasekharan Kothandaraman, Phil Paone, William Tonti
  • Publication number: 20060108662
    Abstract: A fuse structure and method of forming the same is described, wherein the body of the fuse is formed from a crystalline semiconductor body on an insulator, preferably of a silicon-on-insulator wafer, surrounded by a fill-in dielectric. The fill-in dielectric is preferably a material that minimizes stresses on the crystalline body, such as an oxide. The body may be doped, and may also include a silicide layer on the upper surface. This fuse structure may be successfully programmed over a wide range of programming voltages and time.
    Type: Application
    Filed: November 23, 2004
    Publication date: May 25, 2006
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chandrasekharan Kothandaraman, Edward Maciejewski
  • Patent number: 7042094
    Abstract: A multi-level via structure for a semiconductor chip in which the collective area of a vias structure is not entirely oriented directly in-line with the collective area of an adjacent vias structure. In one embodiment, adjacent via structure areas appear to be crisscrossed in relation to one another and in another embodiment adjacent via structure areas do not coincide at all from a perpendicular perspective.
    Type: Grant
    Filed: February 2, 2004
    Date of Patent: May 9, 2006
    Assignee: Infineon Technologies AG
    Inventor: Chandrasekharan Kothandaraman
  • Publication number: 20060087001
    Abstract: A programmable device (eFuse), includes: a substrate (10); an insulator (13) on the substrate; an elongated semiconductor material (12) on the insulator, the elongated semiconductor material having a first end (12a), a second end (12b), a fuse link (11) between the ends, and an upper surface S. The semiconductor material includes a dopant having a concentration of at least 10*17/cc. The first end (12a) is wider than the second end (12b), and a metallic material is disposed on the upper surface. The metallic material is physically migratable along the upper surface responsive to an electrical current I flowable through the semiconductor material and through the metallic material.
    Type: Application
    Filed: October 21, 2004
    Publication date: April 27, 2006
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chandrasekharan Kothandaraman, Subramanian Iyer
  • Patent number: 7029955
    Abstract: A silicided polysilicon based fuse device that is programmable by optical and electrical energy in the polysilicon layer without damage to nearby structures, comprising: a Si substrate; an insulating layer disposed on the substrate; and a fuse device section comprising poly-Si/a silicide/ and a barrier layer, the fuse device section forming an electrical discontinuity in the poly Si layer in response to an electrical pulse or an optical pulse applied to it.
    Type: Grant
    Filed: September 23, 2003
    Date of Patent: April 18, 2006
    Assignee: Infineon Technologies AG
    Inventor: Chandrasekharan Kothandaraman
  • Publication number: 20050167728
    Abstract: An electrically programmable transistor fuse having a double-gate arrangement disposed in a single layer of polysilicon in which a first gate is disposed overlapping a portion of a source region and a second gate is insulated from the first gate and disposed overlapping a portion of a drain region. The first gate includes a terminal for receiving an externally applied control signal and the second gate is capacitively couple to the drain region in which a coupling device is included for increasing the capacitive coupling of the second gate and the drain region for enabling reduction in fuse programming voltage.
    Type: Application
    Filed: January 29, 2004
    Publication date: August 4, 2005
    Inventors: Chandrasekharan Kothandaraman, Danny Shum
  • Publication number: 20050167840
    Abstract: A multi-level via structure for a semiconductor chip in which the collective area of a vias structure is not entirely oriented directly in-line with the collective area of an adjacent vias structure. In one embodiment, adjacent via structure areas appear to be crisscrossed in relation to one another and in another embodiment adjacent via structure areas do not coincide at all from a perpendicular perspective.
    Type: Application
    Filed: February 2, 2004
    Publication date: August 4, 2005
    Inventor: Chandrasekharan Kothandaraman
  • Patent number: 6913954
    Abstract: A fuse device including a transistor having a source, drain, and gate. The gate includes a first and second gate contact. A current may be run from the first gate contact to the second gate contact to heat the gate. The current through the gate indirectly heats the channel region beneath the gate, causing localized annealing of the channel region. The heated gate causes dopants to diffuse from the source and drain into the channel region, permanently changing the properties of the transistor material and programming the fuse device. The fuse device functions as a transistor in an unprogrammed state, and acts as a shunt in a programmed state, caused by the shorting of the source and drain of the transistor during programming.
    Type: Grant
    Filed: June 21, 2004
    Date of Patent: July 5, 2005
    Assignee: Infineon Technologies AG
    Inventor: Chandrasekharan Kothandaraman
  • Patent number: 6828652
    Abstract: A fuse structure (30) formed in a semiconductor device is provided. The fuse structure (30) includes a layer of fuse material (32), a first contact (40), and a second contact (42). The first contact (40) has a first edge (54). At least a portion of the first edge (54) abuts the fuse material layer (32). The second contact (42) has a second edge (55). At least a portion of the second edge (55) abuts the fuse material layer (32). The first edge (54) faces the second edge (55). The first edge (54) is separated from the second edge (55) by a spaced distance (58). A conductive portion of the fuse material layer (32) electrically connects between the first edge (54) and the second edge (55) within the spaced distance (58). The abutting portion of the first edge (54) has a first length. The abutting portion of the second edge (55) has a second length. The first length is greater than the second length.
    Type: Grant
    Filed: May 7, 2002
    Date of Patent: December 7, 2004
    Assignee: Infineon Technologies AG
    Inventor: Chandrasekharan Kothandaraman
  • Publication number: 20040233768
    Abstract: A fuse device including a transistor having a source, drain, and gate. The gate includes a first and second gate contact. A current may be run from the first gate contact to the second gate contact to heat the gate. The current through the gate indirectly heats the channel region beneath the gate, causing localized annealing of the channel region. The heated gate causes dopants to diffuse from the source and drain into the channel region, permanently changing the properties of the transistor material and programming the fuse device. The fuse device functions as a transistor in an unprogrammed state, and acts as a shunt in a programmed state, caused by the shorting of the source and drain of the transistor during programming.
    Type: Application
    Filed: June 21, 2004
    Publication date: November 25, 2004
    Inventor: Chandrasekharan Kothandaraman
  • Patent number: 6781436
    Abstract: A transistor (such as a MOSFET) is operated in its breakdown region, as opposed to its saturation region, to program an electric fuse. With the programming transistor operated in the breakdown region, a much higher current is enabled than the associated saturation current for the same size transistor. Thus, a smaller transistor can be used for programming the fuse. Cooperative with transistor operation in the breakdown region, a dynamic current compliance device is used to limit the peak current to prevent damage than can result from excessive current flowing through the transistor. The current compliance device can be external to the integrated fuse and programming transistor circuit.
    Type: Grant
    Filed: July 25, 2002
    Date of Patent: August 24, 2004
    Assignee: Infineon Technologies AG
    Inventors: Chandrasekharan Kothandaraman, S. Sundar Kumar Iyer
  • Publication number: 20040124458
    Abstract: A fuse device including a transistor having a source, drain, and gate. The gate includes a first and second gate contact. A current may be run from the first gate contact to the second gate contact to heat the gate. The current through the gate indirectly heats the channel region beneath the gate, causing localized annealing of the channel region. The heated gate causes dopants to diffuse from the source and drain into the channel region, permanently changing the properties of the transistor material and programming the fuse device. The fuse device functions as a transistor in an unprogrammed state, and acts as a shunt in a programmed state, caused by the shorting of the source and drain of the transistor during programming.
    Type: Application
    Filed: December 31, 2002
    Publication date: July 1, 2004
    Inventor: Chandrasekharan Kothandaraman
  • Publication number: 20040056703
    Abstract: A transistor (such as a MOSFET) is operated with the well biased, as opposed to being grounded, to program an electric fuse. With the programming transistor operated with an active well bias, more energy is enabled for programming the fuse than is available with a grounded well for the same size transistor. Thus, a smaller transistor can be used of programming the fuse. In a multiple fuse embodiment, the programming transistors can be arranged in the same “well” with a common independent Vbias applied, via a body control circuit, to the entire well during programming of a select fuse.
    Type: Application
    Filed: September 19, 2002
    Publication date: March 25, 2004
    Inventors: Chandrasekharan Kothandaraman, S. Sundar Kumar Iyer
  • Publication number: 20040056325
    Abstract: A silicided polysilicon based fuse device that is programmable by optical and electrical energy in the polysilicon layer without damage to nearby structures, comprising:
    Type: Application
    Filed: September 23, 2003
    Publication date: March 25, 2004
    Inventor: Chandrasekharan Kothandaraman
  • Patent number: 6710640
    Abstract: A transistor (such as a MOSFET) is operated with the well biased, as opposed to being grounded, to program an electric fuse. With the programming transistor operated with an active well bias, more energy is enabled for programming the fuse than is available with a grounded well for the same size transistor. Thus, a smaller transistor can be used of programming the fuse. In a multiple fuse embodiment, the programming transistors can be arranged in the same “well” with a common independent Vbias applied, via a body control circuit, to the entire well during programming of a select fuse.
    Type: Grant
    Filed: September 19, 2002
    Date of Patent: March 23, 2004
    Assignees: Infineon Technologies AG, International Business Machines Corporation
    Inventors: Chandrasekharan Kothandaraman, S. Sundar Kumar Iyer