Patents by Inventor Chandrasekharan Kothandaraman

Chandrasekharan Kothandaraman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100193854
    Abstract: Each of a hot-carrier non-volatile memory device and a method for fabricating the hot carrier non-volatile memory device is predicated upon a semiconductor structure and related method that includes a metal oxide semiconductor field effect transistor structure. The semiconductor structure and related method include at least one of: (1) a spacer that comprises a dielectric material having a dielectric constant greater than 7 (for enhanced hot carrier derived charge capture and retention); and (2) a drain region that comprises a semiconductor material that has a narrower bandgap than a bandgap of a semiconductor material from which is comprised a channel region (for enhanced impact ionization and charged carrier generation).
    Type: Application
    Filed: January 25, 2010
    Publication date: August 5, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Roger Allen Booth, JR., Kangguo Cheng, Chandrasekharan Kothandaraman, Chengwen Pei
  • Publication number: 20100181620
    Abstract: A method of fabricating a memory device is provided that may begin with forming a layered gate stack overlying a semiconductor substrate and patterning a metal electrode layer stopping on the high-k gate dielectric layer of the layered gate stack to provide a first metal gate electrode and a second metal gate electrode on the semiconductor substrate. In a next process sequence, at least one spacer is formed on the first metal gate electrode overlying a portion of the high-k gate dielectric layer, wherein a remaining portion of the high-k gate dielectric is exposed. The remaining portion of the high-k gate dielectric layer is etched to provide a first high-k gate dielectric having a portion that extends beyond a sidewall of the first metal gate electrode and a second high-k gate dielectric having an edge that is aligned to a sidewall of the second metal gate electrode.
    Type: Application
    Filed: January 19, 2009
    Publication date: July 22, 2010
    Applicant: International Business Machines Corporation
    Inventors: Roger A. Booth, JR., Kangguo Cheng, Chandrasekharan Kothandaraman, Chengwen Pei
  • Publication number: 20100181643
    Abstract: A fuse includes a fuse link region, a first region and a second region. The fuse link region electrically connects the first region to the second region. A SiGe layer is disposed only in the fuse link region and the first region.
    Type: Application
    Filed: January 16, 2009
    Publication date: July 22, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chandrasekharan Kothandaraman, Deok-kee Kim, Dureseti Chidambarrao, William K. Henson
  • Patent number: 7750335
    Abstract: A structure including a phase change material and a related method are disclosed. The structure may include a first electrode; a second electrode; a third electrode; a phase change material electrically connecting the first, second and third electrodes for passing a first current through two of the first, second and third electrodes; and a refractory metal barrier heater layer about the phase change material for converting the phase change material between an amorphous, insulative state and a crystalline, conductive state by application of a second current to the phase change material. The structure may be used as a fuse or a phase change material random access memory (PRAM).
    Type: Grant
    Filed: August 16, 2007
    Date of Patent: July 6, 2010
    Assignee: International Business Machines Corporation
    Inventors: Lawrence A. Clevenger, Bruce G. Elmegreen, Deok-Kee Kim, Chandrasekharan Kothandaraman, Lia Krusin-Elbaum, Chung H. Lam, Dennis M. Newns
  • Patent number: 7745855
    Abstract: An integrated eFUSE device is formed by forming a silicon “floating beam” on air, whereupon the fusible portion of the eFUSE device resides. This beam extends between two larger, supporting terminal structures. “Undercutting” techniques are employed whereby a structure is formed atop a buried layer, and that buried layer is removed by selective etching. Whereby a “floating” silicide eFUSE conductor is formed on a silicon beam structure. In its initial state, the eFUSE silicide is highly conductive, exhibiting low electrical resistance (the “unblown state of the eFUSE). When a sufficiently large current is passed through the eFUSE conductor, localized heating occurs. This heating causes electromigration of the silicide into the silicon beam (and into surrounding silicon, thereby diffusing the silicide and greatly increasing its electrical resistance. When the current source is removed, the silicide remains permanently in this diffused state, the “blown” state of the eFUSE.
    Type: Grant
    Filed: October 4, 2007
    Date of Patent: June 29, 2010
    Assignee: International Business Machines Corporation
    Inventors: William K. Henson, Deok-Kee Kim, Chandrasekharan Kothandaraman, Byeongju Park
  • Patent number: 7732893
    Abstract: The present invention provides an electrical fuse structure for achieving a post-programming resistance distribution with higher resistance values and to enhance the reliability of electrical fuse programming. A partly doped electrical fuse structure with undoped semiconductor material in the cathode combined with P-doped semiconductor material in the fuselink and anode is disclosed and the data supporting the superior performance of the disclosed electrical fuse is shown.
    Type: Grant
    Filed: March 7, 2007
    Date of Patent: June 8, 2010
    Assignee: International Business Machines Corporation
    Inventors: Subramanian S. Iyer, Deok-Kee Kim, Chandrasekharan Kothandaraman, Byeongju Park
  • Patent number: 7713792
    Abstract: A fuse structure, a method for fabricating the fuse structure and a method for programming a fuse within the fuse structure each use a fuse material layer that is used as a fuse, and located upon a monocrystalline semiconductor material layer in turn located over a substrate. At least part of the monocrystalline semiconductor material layer is separated from the substrate by a gap. Use of the monocrystalline semiconductor material layer, as well as the gap, provides for enhanced uniformity and reproducibility when programming the fuse.
    Type: Grant
    Filed: October 10, 2007
    Date of Patent: May 11, 2010
    Assignee: International Business Machines Corporation
    Inventors: Anil Kumar Chinthakindi, Deok-Kee Kim, Chandrasekharan Kothandaraman, Byeongju Park
  • Patent number: 7714326
    Abstract: The present invention provides structures for antifuses that utilize electromigration for programming. By providing a portion of antifuse link with high resistance without conducting material and then by inducing electromigration of the conducting material into the antifuse link, the resistance of the antifuse structure is changed. By providing a terminal on the antifuse link, the change in the electrical properties of the antifuse link is detected and sensed. Also disclosed are an integrated antifuse with a built-in sensing device and a two dimensional array of integrated antifuses that can share programming transistors and sensing circuitry.
    Type: Grant
    Filed: March 7, 2007
    Date of Patent: May 11, 2010
    Assignee: International Business Machines Corporation
    Inventors: Deok-kee Kim, Hoki Kim, Chandrasekharan Kothandaraman, Byeongju Park, John M. Safran
  • Publication number: 20100032732
    Abstract: An electrical antifuse comprising a field effect transistor includes a gate dielectric having two gate dielectric portions. Upon application of electric field across the gate dielectric, the magnitude of the electrical field is locally enhanced at the boundary between the thick and thin gate dielectric portions due to the geometry, thereby allowing programming of the electrical antifuse at a lower supply voltage between the two electrodes, i.e., the body and the gate electrode of the transistor, across the gate dielectric.
    Type: Application
    Filed: August 6, 2008
    Publication date: February 11, 2010
    Applicant: International Business Machines Corporation
    Inventors: Roger A. Booth, JR., Kangguo Cheng, Chandrasekharan Kothandaraman, Chengwen Pei, Ravi M. Todi, Xiaojun Yu
  • Patent number: 7633079
    Abstract: A programmable phase change material (PCM) structure includes a heater element formed at a BEOL level of a semiconductor device, the BEOL level including a low-K dielectric material therein; a first via in electrical contact with a first end of the heater element and a second via in electrical contact with a second end of the heater element, thereby defining a programming current path which passes through the first via, the heater element, and the second via; a PCM element disposed above the heater element, the PCM element configured to be programmed between a lower resistance crystalline state and a higher resistance amorphous state through the use of programming currents through the heater element; and a third via in electrical contact with the PCM element, thereby defining a sense current path which passes through the third via, the PCM element, the heater element, and the second via.
    Type: Grant
    Filed: September 6, 2007
    Date of Patent: December 15, 2009
    Assignee: International Business Machines Corporation
    Inventors: Kuang-Neng Chen, Bruce G. Elmegreen, Deok-Kee Kim, Chandrasekharan Kothandaraman, Lia Krusin-Elbaum, Chung H. Lam, Dennis M. Newns, Byeongju Park, Sampath Purushothaman
  • Publication number: 20090283840
    Abstract: A semiconductor structure and a method for fabricating the semiconductor structure provide a field effect device located and formed upon an active region of a semiconductor substrate and at least one of a fuse structure, an anti-fuse structure and a resistor structure located and formed at least in part simultaneously upon an isolation region laterally separated from the active region within the semiconductor substrate. The field effect device includes a gate dielectric comprising a high dielectric constant dielectric material and a gate electrode comprising a metal material. The at least one of the fuse structure, anti-fuse structure and resistor structure includes a pad dielectric comprising the same material as the gate dielectric, and optionally, also a fuse, anti-fuse or resistor that may comprise the same metal material as the gate electrode.
    Type: Application
    Filed: May 13, 2008
    Publication date: November 19, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Douglas D. Coolbaugh, Ebenezer E. Eshun, Ephrem G. Gebreselasie, Zhong-Xiang He, Herbert Lei Ho, Deok-kee Kim, Chandrasekharan Kothandaraman, Dan Moy, Robert Mark Rassel, John Matthew Safran, Kenneth Jay Stein, Norman Whitelaw Robson, Ping-Chuan Wang, Hongwen Yan
  • Publication number: 20090267179
    Abstract: A system in one embodiment includes a multiprocessor chip comprising a plurality of cores; a plurality of power circuits, each power circuit being coupled to one of the cores; and an electrically programmable fuse in each power circuit. Each electrically programmable fuse further comprises a first electrode coupled to the associated power circuit; a second electrode coupled to the associated power circuit; a first pad coupled to the first electrode; a second pad coupled to the second electrode; and an electrically conductive material extending between the first and second electrodes and forming part of the associated power circuit, the electrically conductive material being characterized as tending to electromigrate from one of the electrodes to the other electrode under an applied electrical current passing between the electrodes, wherein the electromigration increases an overall resistance of the power circuit.
    Type: Application
    Filed: April 24, 2008
    Publication date: October 29, 2009
    Applicant: International Business Machines Corporation
    Inventors: Subramanian S. Iyer, Babar Ali Khan, Chandrasekharan Kothandaraman, Norman Whitelaw Robson
  • Patent number: 7583125
    Abstract: An integrated circuit device having at least one fuse capable of being blown in order to provide measurements of fuse current-voltage characteristics is provided. The integrated circuit device also provides at least one pulse generation circuit associated with the fuse and capable of generating a pulse to blow the fuse through one or more DC input signals.
    Type: Grant
    Filed: October 25, 2007
    Date of Patent: September 1, 2009
    Assignee: International Business Machines Corporation
    Inventors: Manjul Bhushan, Mark B. Ketchen, Chandrasekharan Kothandaraman, Edward P. Maciejewski
  • Patent number: 7566593
    Abstract: A fuse structure comprises a cavity interposed between a substrate and a fuse material layer. The cavity is not formed at a sidewall of the fuse material layer, or at a surface of the fuse material layer opposite the substrate. A void may be formed interposed between the substrate and the fuse material layer while using a self-aligned etching method, when the fuse material layer comprises lobed ends and a narrower middle region. The void is separated by a pair of sacrificial layer pedestals that support the fuse material layer. The void is encapsulated to form the cavity by using an encapsulating dielectric layer. Alternatively, a block mask may be used when forming the void interposed between the substrate and the fuse material layer.
    Type: Grant
    Filed: October 3, 2006
    Date of Patent: July 28, 2009
    Assignee: International Business Machines Corporation
    Inventors: Anil K. Chinthakindi, Deok-kee Kim, Chandrasekharan Kothandaraman
  • Publication number: 20090179302
    Abstract: A programmable device (eFuse), includes: a substrate (10); an insulator (13) on the substrate; an elongated semiconductor material (12) on the insulator, the elongated semiconductor material having a first end (12a), a second end (12b), a fuse link (11) between the ends, and an upper surface S. The semiconductor material includes a dopant having a concentration of at least 10*17/cc. The first end (12a) is wider than the second end (12b), and a metallic material is disposed on the upper surface. The metallic material is physically migratable along the upper surface responsive to an electrical current I flowable through the semiconductor material and through the metallic material.
    Type: Application
    Filed: January 16, 2009
    Publication date: July 16, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chandrasekharan Kothandaraman, Subramanian Iyer
  • Patent number: 7550789
    Abstract: Techniques and systems whereby operation of and/or access to particular features of an electronic device may be controlled after the device has left the control of the manufacturer are provided. The operation and/or access may be provided based on values stored in non-volatile storage elements, such as electrically programmable fused (eFUSES).
    Type: Grant
    Filed: February 29, 2008
    Date of Patent: June 23, 2009
    Assignee: International Business Machines Corporation
    Inventors: Anthony R. Bonaccio, Karl R. Erickson, John A. Fifield, Chandrasekharan Kothandaraman, Phil C. Paone, William R. Tonti
  • Patent number: 7550323
    Abstract: A metal layer is deposited on the patterned semiconductor material layer containing a cathode semiconductor portion, a fuselink semiconductor portion, and an anode semiconductor portion. The metal layer may be patterned so that a middle portion of the fuselink semiconductor portion has a thin metal layer, which upon annealing produces a thinner metal semiconductor alloy portion than surrounding metal semiconductor alloy portion on the fuselink semiconductor portion. Alternatively, a middle portion of the metal semiconductor alloy having a uniform thickness throughout the fuselink may be lithographically patterned and etched to form a thin metal semiconductor alloy portion in the middle of the fuselink, while thick metal semiconductor alloy portions are formed on the end portions of the fuselink. The resulting inventive electrical fuse has interfaces at which a thinner metal semiconductor alloy abuts a thicker metal semiconductor alloy in the fuselink to enhance the divergence of electrical current.
    Type: Grant
    Filed: August 8, 2007
    Date of Patent: June 23, 2009
    Assignee: International Business Machines Corporation
    Inventors: Dureseti Chidambarrao, William K. Henson, Deok-kee Kim, Chandrasekharan Kothandaraman
  • Publication number: 20090141533
    Abstract: A metal layer and a semiconductor layer are sequentially deposited on a substrate. The semiconductor layer and the metal layer are lithographically patterned to form a stack of a semiconductor portion and a metal gate portion, which is preferably performed concurrently with formation of at least one metal gate stack. In one embodiment, the size of the semiconductor portion is reduced and a metal semiconductor alloy portion is formed on the semiconductor portion by metallization. In a first electrical antifuse formed thereby, the metal semiconductor alloy portion may be electromigrated to form a short between the metal semiconductor alloy portion and the metal gate portion. In another embodiment, two disjoined metal semiconductor alloy portions are formed on the semiconductor portion. In a second electrical antifuse formed thereby, the metal semiconductor alloy portion may be electromigrated to form a short between the two previously disjoined metal semiconductor alloy portions.
    Type: Application
    Filed: November 29, 2007
    Publication date: June 4, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Deok-kee Kim, Chandrasekharan Kothandaraman, Dan Moy, Norman W. Robson, John M. Safran, Kenneth J. Stein
  • Publication number: 20090108396
    Abstract: A contiguous block of a stack of two heterogeneous semiconductor layers is formed over an insulator region such as shallow trench isolation. A portion of the contiguous block is exposed to an etch, while another portion is masked during the etch. The etch removes an upper semiconductor layer selective to a lower semiconductor layer in the exposed portion. The etch mask is removed and the entirety of the lower semiconductor layer within the exposed region is metallized. A first metal semiconductor alloy vertically abutting the insulator region is formed, while exposed surfaces of the stack of two heterogeneous semiconductor layers, which comprises the materials of the upper semiconductor layer, are concurrently metallized to form a second metal semiconductor alloy. An inflection point for current and, consequently, a region of flux divergence are formed at the boundary of the two metal semiconductor alloys.
    Type: Application
    Filed: October 26, 2007
    Publication date: April 30, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dureseti Chidambarrao, William K. Henson, Deok-Kee Kim, Chandrasekharan Kothandaraman
  • Publication number: 20090101989
    Abstract: A dielectric material layer is formed on a metal gate layer for a metal gate electrode, and then lithographically patterned to form a dielectric material portion, followed by formation of a polycrystalline semiconductor layer thereupon. A semiconductor device employing a metal gate electrode is formed in a region of the semiconductor substrate containing a vertically abutting stack of the metal gate layer and the polycrystalline semiconductor layer. A material stack in the shape of an electrical fuse is formed in another region of the semiconductor substrate containing a vertical stack of the metal gate layer, the dielectric material portion, and the polycrystalline semiconductor layer. After metallization of the polycrystalline semiconductor layer, an electrical fuse containing a polycrystalline semiconductor portion and a metal semiconductor alloy portion is formed over the dielectric material portion that separates the electrical fuse from the metal gate layer.
    Type: Application
    Filed: October 18, 2007
    Publication date: April 23, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Xiangdong Chen, Deok-kee Kim, Chandrasekharan Kothandaraman