Abstract: An optical cable including a rollable optical fiber ribbon is provided. The optical cable includes a plurality of loose tubes, and a plurality of rollable optical fiber ribbons are disposed inside each loose tube. A plurality of loose tubes are disposed at the periphery of the central strength member. The length of each rollable optical fiber ribbon disposed inside the loose tube is 1% or more longer than the length of the corresponding loose tube. Compared to an optical cable including a conventional ribbon, the optical fiber has a higher density and preferred transmission performance.

Abstract: An optical cable including a rollable optical fiber ribbon is provided. The optical cable includes a plurality of loose tubes, and a plurality of rollable optical fiber ribbons are disposed inside each loose tube. A plurality of loose tubes are disposed at the periphery of the central strength member. The length of each rollable optical fiber ribbon disposed inside the loose tube is 1% or more longer than the length of the corresponding loose tube. Compared to an optical cable including a conventional ribbon, the optical fiber has a higher density and preferred transmission performance.

Abstract: Provided are a conductive composite, and a method of manufacturing the conductive composite, the composite comprising nonconductive hollow microspheres and conductive filler which are dispersed in a matrix. The nonconductive hollow microspheres and the conductive filler comprised in the conductive composite may be expanded or deformed by pressurization or thermal treatment.

Abstract: A vertical alignment method for a radar of a vehicle includes the steps of radiating radio wave to a forward ground by a radar which is installed on the vehicle; receiving reflected wave which is reflected from the ground; and determining whether or not a vertical misalignment of the radar occurs, based on the reflected wave.

Abstract: A method of determining the presence of type II pyrethroid compounds in a sample.

Abstract: A vertical alignment method for a radar of a vehicle includes the steps of radiating radio wave to a forward ground by a radar which is installed on the vehicle; receiving reflected wave which is reflected from the ground; and determining whether or not a vertical misalignment of the radar occurs, based on the reflected wave.

Abstract: A headlamp control device for a vehicle is provided. The device includes a front sensor, a wheel speed sensor, an Electrical Control Unit (ECU), a first ballaster, a second ballaster, a relay switch, and a power supply switch. The front sensor senses a target vehicle. The wheel speed sensor detects a speed of a reference vehicle. The ECU outputs a switching control signal. The first ballaster generates a first boosting voltage. The second ballaster generates a second boosting voltage. The relay switch supplies an internal voltage to first and second high-beam lamps, or first and second ballasters. The power supply switch turns on in response to a switching control signal.

Abstract: A system and method for load balancing transmissions across a multilink frame relay connection is disclosed. A credit value is assigned to each bundle link in the multilink based on the amount of data transmitted over a set period of time. Frames or frame fragments are sent over the link with the highest credit value. Credit is subtracted from the link in proportion to the size of the frame or frame fragment. When two or more links have the same credit value, the frame or fragment is sent over the slowest link. The credit values are reset when a specified time period has passed, a link has a negative credit value, or all the links have a credit value of zero.

Abstract: A distribution pattern is established to distribute multilink frame relay (MFR) fragments. The distribution pattern includes a sequence of link entries associated with links in a link bundle. A number of link entries in the distribution pattern is determined by dividing a total link speed of the link bundle by a minimum possible link speed supported by a system. Each link entry is placed in the distribution pattern when the associated link is capable of transmitting a current fragment in a fastest transmit time. The fastest transmit time is determined based on the link speed of the link and a transmit time for the link to transmit other fragments previously allocated to that link. The fragments are distributed to the links in the link bundle according to the distribution pattern from a first link entry to a last link entry in the distribution pattern. The distribution pattern is repeated after the last link entry.

Abstract: There are provided an ultra thin film silicon on insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) having a recessed source/drain structure, and a method of fabricating the same.

Abstract: A transistor using impact ionization and a method of manufacturing the same are provided. A gate dielectric layer, a gate, and first and second spacers are formed on a semiconductor substrate. A first impurity layer is formed spaced from the first spacer and a second impurity layer is formed expanding and overlapping with the second spacer therebelow, by performing slant ion-implantation on the semiconductor substrate using the gate and the first and second spacers as a mask. A source and a drain are formed on the semiconductor substrate to be self-aligned with the first and second spacers, respectively, thereby defining an ionization region between the source and the drain in the semiconductor substrate. The source includes a first silicide layer to form a schottky junction with the ionization region.

Abstract: A non-volatile memory device using mobile ionic charges and a method of manufacturing the same are provided. The method includes forming a gate dielectric layer on a semiconductor substrate, injecting mobile ionic charges into the gate dielectric layer by leading source plasma to a surface of the gate dielectric layer and implanting ions within the source plasma into the gate dielectric layer using plasma doping, forming on the gate dielectric layer a gate to which a control voltage controlling distribution of the mobile ionic charges within the gate dielectric layer is supplied to control a threshold voltage, and forming a source region and a drain region in the semiconductor substrate near the gate.

Abstract: Provided is a secondary battery having an electrode assembly installed in a battery case made up of a laminated sheet composed of an outer coating layer of a polymer film, a barrier layer of a metal foil and an inner sealant layer of a polyolefin material, wherein the metal foil of the barrier layer is formed of an aluminum alloy, the outer coating layer is formed of polyethylene naphthalate (PEN) and/or the outer surface of the outer coating layer is provided with a polyethylene naphthalate (PET) layer, and wherein the battery has a nail penetration resistance force of more than 6.5 kgf. The battery in accordance with the present invention exhibits further improved safety due to the ability to significantly reduce the probability of invasion, ignition or explosion as compared to conventional batteries, even when the battery is exposed to external physical impact or is pressed by sharp objects.

Abstract: The present invention relates to nucleoside derivatives represented by general formulas I and II, their synthetic methods and their pharmacologically acceptable salts thereof, and compositions containing such compounds. Methods for treating hyperproliferative disorders by administering the compounds are also included.

Abstract: The present invention provides a battery having a structure for increasing the power storage capacity and output thereof In accordance with the present invention, in a battery comprising an electrode assembly including anode plates, cathode plates and separators; and a battery case, both side bonding portions of which are folded toward adjacent sides thereof, for accommodating the electrode assembly and a designated amount of electrolyte, and sealing the electrode assembly such that two electrode terminals connected to corresponding electrode taps of the anode and cathode plates of the electrode assembly are exposed to the outside, an upper bonding portion of the battery case is folded toward the upper end of the battery case, and/or common portions of the upper bonding portion and both side portions of the battery case are cut off, and/or inner corners corresponding to the upper bonding portion have larger radiuses of curvature, and/or receipt portions for receiving the electrode assembly are respectively fo

Abstract: Quinazoline derivatives represented by the general formula pharmacologically acceptable salts thereof, and compositions containing such compounds are described. Methods for using the compounds for treatment of hyperproliferative disorders are also described.

Abstract: Provided is a cell wherein out of electrodes constituting the cell, the outermost two electrodes are both cathodes, cathode current collectors of the cathodes are single-side coated with cathode active materials on the first surfaces thereof, other sides of cathode current collectors non-coated with cathode active materials are disposed toward the outside of a cell assembly and the thickness of cathode current collectors is 70 to 150% of that of the cathode active material coated layer. The cell in accordance with the present invention exhibits excellent safety in a nail penetration test.

Abstract: A semiconductor memory test apparatus includes a test signal input unit for externally receiving a test word line model signal and a test column address pulse enable signal, which are used for a memory operation in the test mode. The test apparatus also includes a test mode setting unit that receives: a row address strobe bar signal, a column address strobe bar signal, a write enable bar signal and an address signal, and that generates first and second test mode setting signals. A first switching unit switches a signal input from a row address path circuit or from the test signal input unit, in accordance with a first test mode setting signal. A second switching unit switches another signal input from the row address path circuit or from the test signal input unit in accordance with a second test mode setting signal, and outputs the switched signal to the column address path circuit.

Abstract: A semiconductor memory apparatus having a refresh test circuit provided with a control unit, a write control unit, a row address buffer and column address buffer, a refresh address counter, a refresh control unit, a column decoder, a data input/output buffer, a plurality of sense amplifier arrays and a plurality of memory cell arrays, includes a refresh test control unit for receiving an address signal by the control of the control unit and controlling the refresh control unit, the row block decoder and the plurality of sense amplifier arrays. The apparatus screens refresh-related poor products by efficiently applying a disturb refresh test during a short period of time.

Abstract: A redundancy circuit for a semiconductor integrated circuit is disclosed, which includes each cell of the column redundancy cell block corresponding to each cell of the cell sub-array is connected opposite to the connection of the cells of the cell sub-array, wherein a state that an electric charge corresponding to a data written into each cell of the cell sub-array and the column redundancy cell block is discharged, is measured for thus accurately checking the position of the repaired cell after the redundancy operation is performed.